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3 results on '"Dai Nakamura"'

1. 13.1 A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology

Author

J. Zhou, Teruo Takagiwa, Toshifumi Hashimoto, Y. Ochi, Toshiki Hisada, Mario Sako, Takahiro Yamashita, M. Uda, Takatoshi Minamoto, Hiroshi Sugawara, T. Kawabe, Noboru Shibata, N. Raghunathan, Junichi Sato, Koji Hosono, Osamu Nagao, T. Ogawa, Naoki Kobayashi, T. Someya, Shuo Chen, Ryo Fukuda, Koichi Kawakami, H. Date, Makoto Miakashi, Y. Matsumoto, Takahiro Shimizu, M. Sato, J. Nakai, Naohito Morozumi, M. Ogawa, Tomoharu Hashiguchi, Tomohiro Sugimoto, H. Takamoto, T. Nakano, T. Nakagawa, Masami Masuda, T. Shibuya, M. Kojima, Hiroshi Nakamura, H. Nasu, Kosuke Yanagidaira, Kiyofumi Sakurai, Yasushi Nagadomi, Kazuaki Kawaguchi, Yasuyuki Kajitani, Kazushige Kanda, Junji Musha, Ryoichi Tachibana, T. Kaneko, Y. L. Koh, Juan Lee, and Dai Nakamura

Subjects
010302 applied physics, Hardware_MEMORYSTRUCTURES, Memory chip, business.industry, Computer science, 4-bit, 01 natural sciences, Flash memory, Flash (photography), Reliability (semiconductor), 0103 physical sciences, Layer (object-oriented design), Line (text file), 010306 general physics, business, Computer hardware, Word (computer architecture)
Abstract

Since 3D-Flash memory took over for 2D-Flash memory, chip capacity has continuously improved [1]–[3]. In the 2D-Flash era, 2b/cell (MLC) offered higher performance and reliability, while a 3b/cell (TLC) offered the lowest cost. Thanks to a larger feature size, 3D Flash cell reliability is much better than that of 2D. As a result, TLC 3D-Flash became the mainstream non-volatile memory, since it satisfies most market requirements in both performance and reliability. To meet the continuously growing market demand for higher capacity and lower cost, a 4b/cell (QLC) 3D-Flash memory in a 96-WL-layer technology is presented. It achieves an 8.5Gb/mm2 area capacity, which is $42 \sim 50$% greater than the 3D-Flash memory reported in [2], [3]. A chip micrograph and a table summarizing key features is shown in Fig. 13.1.7. The total 1.33Tb capacity is the highest single Flash memory chip capacity reported thus far.

Published
2019
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2. A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology

Author

Eiichi Makino, Rieko Tanaka, Masaaki Higashitani, Hiromitsu Komai, Dai Nakamura, Kiyomi Naruke, Brian Murphy, Yoshikazu Hosomura, T. Ogawa, Junji Musha, Mai Muramoto, Ayako Yuminaka, G. Hemink, Yoshihiko Shindo, Yasuhiko Matsunaga, Yosuke Kato, Toshiaki Edahiro, Kiyofumi Sakurai, Naoaki Kanagawa, M. Watanabe, Hitoshi Shiga, Bo Lei, Koichi Fukuda, Naoya Tokiwa, Toru Miwa, Koichi Kawakami, Go Shikata, Takatoshi Minamoto, Junpei Sato, Hong Ding, Makoto Iwai, Alex Mak, Manabu Sakai, Teruo Takagiwa, Osamu Nagao, Takahiko Hara, Masaru Nakamichi, Dana Lee, Yuya Suzuki, Yuka Furuta, Kosuke Yanagidaira, and Yoshihisa Watanabe

Subjects
Hardware_MEMORYSTRUCTURES, Computer science, Nand flash memory, business.industry, NAND gate, USB, Flash memory, law.invention, Flash (photography), CMOS, law, Server, Embedded system, business, Computer hardware, Computer memory, Flash file system
Abstract

NAND flash memories are now indispensable for our modern lives. The application range of the storage memory devices began with digital still cameras and has been extended to USB memories, memory cards, MP3 players, cell phones including smart phones, netbooks, and so on. This is because higher storage capacity and lower cost are realized through means of technology scaling every year. Emerging markets, such as solid-state drives (SSDs) and data-storage servers, require lower bit cost, higher program and read throughputs, and lower power consumption

Published
2011
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3. A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology

Author

Norifumi Kajimura, H. Otake, F. Ito, Kazushige Kanda, Y. Okukawa, Teruhiko Kamei, Mitsuhiro Noguchi, M. Higashitani, M. Kojima, Masahiro Yoshihara, Kazuhide Yoneya, Frank Tsai, Masanobu Shirakawa, M. Itoh, Siu Lung Chan, Toshiki Hisada, Yosuke Kato, Takashi Taira, Eiichi Makino, Binh Quang Le, Dai Nakamura, G. Hemink, Toshio Yamamura, Alex Mak, Shinji Miyamoto, Raul-Adrian Cernea, Yoshinao Suzuki, Shigeo Ohshima, Susumu Fujimura, Koji Hosono, Toru Miwa, Yoshiaki Takeuchi, T. Maruyama, T. Arizono, Toshitake Yaegashi, Masaru Koyanagi, and K. Ino

Subjects
Engineering, Hardware_MEMORYSTRUCTURES, business.industry, Nand flash memory, % area reduction, NAND gate, CMOS, Hardware_GENERAL, Charge trap flash, business, Computer hardware, Gate equivalent, Leakage (electronics), Voltage
Abstract

NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.

Published
2008
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