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We present a scalable Software-Defined-Networking (SDN) control-plane to integrate Silicon Photonics (SiP) with conventional Ethernet/InfiniBand networks and simultaneously perform packet and circuit switching. Experimental evaluations demonstrate this unique solution with 224 microseconds control plane latency for data-center and high-performance-computing platforms.

We present an architecture towards accelerating compute element operations on a fully arbitrated silicon photonic (SiP) system. An 8×8 SiP network is controlled in a distributed fashion, with connectivity consisting of two 10Gbps wavelength division multiplexed data links that are arbitrated out-of-band.

A scalable and flexible memory interconnect is a key component for a many-core architecture to take full advantage of the high-bandwidth of multiple memory stacks. In this paper, we discuss both technological and architectural challenges of these processor-to-memory interconnects, and focus on two important issues of many-core memory accesses: traffic hotspots and non-uniform memory access (NUMA). We propose a reconfigurable Silicon photonic memory interconnect based on 2.5D stacking that can direct memory traffic to any memory interface on the processor, thus alleviating the two aforementioned effects in addition to providing high bandwidth. Simulations based on a 16-core 4-memory model show that the proposed architecture can lead to up to 2× STREAM speedup over fixed connections in both hotspot and NUMA scenarios. We also demonstrate the proposed architecture using a four-port Silicon photonic demultiplexer and a 4×4 synthesizable on-chip fabric called OpenSoC. The FPGA-emulated system demonstrates dynamic memory rewiring through wavelength routing, and achieves a reconfiguration time of 5 microseconds.

We review the requirements and expectations of future Supercomputer architectures, analyse how transparent optical networking might contribute to these future systems scalable performance, and develop the most immediate challenges for optical system developers in this context.

Optical interconnects, which support the transport of large bandwidths over warehouse-scale distance, can help to further scale data-movement capabilities in high performance computing (HPC) platforms. However, due to the circuit switching nature of optical systems and additional peculiarities, such as sensitivity to temperature and the need for wavelength channel locking, optical links generally show longer link initialization delays. These delays are a major obstacle in exploiting the high bandwidth of optics for application speedups, especially when low-latency remote direct memory access (RDMA) is required or small messages are used. These limitations can be overcome by maintaining a set of frequently used optical circuits based on the temporal locality of the application and by maximizing the number of reuses to amortize initialization overheads. However, since circuits cannot be simultaneously maintained between all source-destination pairs, the set of selected circuits must be carefully managed. This paper applies techniques inspired by cache optimizations to intelligently manage circuit resources with the goal of maximizing the circuit successful 'hit' rate. We propose the concept of "circuit reuse distance" and design circuit replacement policies based on this metric. We profile the reuse distance based on a group of representative HPC applications with different communications patterns and show the potential to amortize circuit setup delay over multiple circuit requests. We then develop a Markov transition matrix based reuse distance predictor and two circuit replacement policies. The proposed predictor provides significantly higher accuracy than traditional maximum likelihood prediction and the two replacement policies are shown to effectively increase the hit rate compared to the Least Recently Used policy. We further investigate the tradeoffs between the realized hit rate and energy consumption. Finally, the feasibility of the proposed concept is experimentally demonstrated using silicon photonic devices in an FPGA-controlled network test bed.

We present an optical programmable network architecture to enable agile and efficient iterative multicasting for cluster computing framework. Support for multiple multicast groups and dynamic group reassignment are experimentally demonstrated.

iOS is Apple's mobile operating system and is presently used on the iPhone, iPad, and iPod Touch. The hardware platforms associated with the iOS operating system provide a powerful platform for sensor applications. In this paper, we provide a case study on the development of a digital multimeter (DMM) using an iPod Touch. The DMM case study addresses the major subsystems (hardware, software, and firmware) of a typical sensor platform and specific advantages of implementation using an iOS device.