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A Time-Domain Resistance-to-Digital Converter (RDC) with a referential 1-bit ΔΣ Modulated variable resistor is proposed. The proposed RDC converts an input resistance to a frequency and compares a referential variable resistor to decrease a sensor read-out error caused by a non-linearity of an oscillation frequency. A 1-bit ΔΣ modulated variable resistor is demodulated by an oscillator and a counter. Hence a low-pass filter circuit is not required. In addition, non-linearity canceling feedback is proposed to decrease comparison time. This prototype RDC achieves 10.1bits conductance resolution at 1kSps in 10μS to 110μS full-scale range.

This paper describes an energy-efficient BJT-based temperature-to-digital converter (TDC) with a state-of-the-art resolution FoM (RFoM) of 5.4pJ·K2. It consists of a BJT front-end, a capacitively-coupled instrumentation amplifier (CCIA) and a 2nd-order continuous-time (CT) ΔΣADC. The front-end and the CCIA employ bitstream-controlled dynamic element matching (DEM) and chopping to mitigate mismatch and 1/f noise without incurring quantization noise fold-back. The sensor achieves ±0.13°C (3σ) inaccuracy from -40 to 125°C and has a supply sensitivity of 8.2mK/V.

This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a resistance-controlled-oscillator. The TDC is used to measure the fractional part of oscillation period, which realize a high resolution and conversion rate with moderate oscillation frequency. Proposed fractional period estimation technique reduce the required number of TDC and save power consumption. A prototype system was developed and 23 ppm resolution of resistance change at conversion rate of 5kSps was experimentally demonstrated.

This paper presents an ultra-low-power intersignal time-delay-to-digital converter. It introduces polarity-coincidence adaptive time-delay estimation, a mixed-signal processing technique that consumes only 78.2nW for a 3-channel delay estimation. A 0.18um CMOS implementation of the converter has been tested and characterized with controlled and real-life stimuli. This analog-to-feature converter has further been used to estimate the time difference of arrival in an audio-based vehicle-bearing IoT system.

Oil palm is one of the famous commercial crops of Thailand. The production is in the 3th rank of the south east Asia, and plantation is still increasing every year. To investigate the feasibility of using electrical capacitance measuring technique as an alternative method for low-cost non-destructive, oil palm fresh oil (CPO) and water have been prepared and studied. One group is concerned with the immiscible fluid and another is all ultrasonic shakes. The mass concentration (x) of CPO varied from 0 g/cm3 to 0.9 g/cm3 and then all experiments were tested on room temperature (25oC). Guard parallel structure has been used in conjunction with AD7747 capacitive to digital converter to obtain capacitance value (y). The results show that y = 0.11987x2 − 0.46104x + 0.47418 with r2 = 0.98098. The model for second sample is y = 0.08965x2 − 0.41335x + 0.3731 with r2 = 0.9554. The capacitance of first sample is higher than the second sample. As previously mentioned, this project aims to make benefit of interest on seasonable optimistic harvests.

A displacement-to-digital converter (DDC) based on inductive (eddy-current) sensor is presented. The sensor is embedded in a self-oscillating front-end, whose 145MHz output is then digitized by a ratiometric ΔΣ ADC. Over a 10μm range, the DDC achieves 1.85nm resolution (1.02 pH), in a 2kHz bandwidth. It draws 9.1mW from a 1.8 V supply making it the most energy-efficient ECS interface ever reported.

This paper presents the most accurate BJT-based CMOS temperature-to-digital converter (TDC) ever reported, with an inaccuracy of ±60mK (3σ) from −70°C to 125°C. This is 2× better than the state-of-the-art, despite being implemented in a process (160nm) that only offers low-β F ( F -compensation scheme, the use of dynamic error correction techniques to suppress non-BJT related errors and the use of an energy-efficient zoom-ADC based on current-reuse OTAs. These techniques also result in very low power-supply sensitivity (12mK/V), thus maintaining TDC accuracy for supply voltages ranging from 1.5V to 2V.

Precision MEMS oscillators require a temperature-to-digital converter (TDC) that adjusts the multiplication factor of a fractional-N PLL in order to compensate for the MEMS resonator's frequency variation over temperature [1]. This compensation, however, provides a path for the TDC's noise to propagate to the oscillator's output as phase noise (PN). Previous work has sought to minimize this noise, by using high-resolution TDCs, e.g., the MEMS-thermistor based TDC described in [1]. This paper presents a TDC based on dual-MEMS resonators [2–3] that has no significant impact on oscillator PN. In a 130Hz bandwidth (BW), the sensor achieves a thermal-noise-limited resolution of 40µK, leading to a resolution FOM (Energy/Conversion × Resolution2) of 0.12pJK2, 5× better than the state of the art [4].

A novel on-chip four-bit transient-to-digital converter with a single RC-based detection for system-level electrostatic discharge (ESD) protection design is proposed in this paper. The proposed transient to digital converter is designed to detect ESD-induced transient disturbances and transfer different ESD voltages into digital codes under system-level ESD tests. This work is simulated in a 65-nm CMOS process using a 2.5 V supply voltage. The simulation results show the correctness of the circuit function and effectively distinguish different voltage disturbances.

This work presents the design and simulation of a low power CMOS Sample and Hold OTA for a 16bit, 5Ms/S pipelined ADC. The designing of high precision amplifiers is challenging in modern CMOS process. It drives ADC design methodology towards advance calibration approaches and compromised with low SNR. This paper deals with advance design techniques for High gain like triple cascode and achieves a DC gain of 132 dB and 68 MHz unity gain bandwidth with a phase margin of 88 degrees while driving the 16pf load of the first stage. Transient response of Charge Redistribution SHA shows settling accuracy of 15uV in 66 nanoseconds while consuming 20mW power. Switched capacitor CMFB has been implemented for the gain boosting amplifiers and main stage amplifier respectively. The design has been implemented in UMC 0.18μm technology. Design methodology for high gain and better settling performance at low power are also discussed in detail.

Direct Digital Converter (DDC) suitable for resistive sensor elements connected in the form of bridge provides a digital output proportional to quantity being sensed. However, such a DDC requires that all the four sensor elements are to be identical. If there is a mismatch between the sensor elements (nominal values of the four resistances not equal) the error in the output of the DDC increases drastically. We now present a modified DDC that can tolerate mismatch between the four sensing elements of a bridge type resistive sensor. While the worst case error observed from the conventional DDC scheme rises from ± 0.07% to ± 1.32 % (simulation studies) for a very low mismatch of 0.03 %, the worst case error observed from the improved DDC scheme proposed here is only ± 0.24%.

Frequency-modulated operation of MEMS gyroscopes promises numerous benefits, including inherently accurate scale factor, improved bias stability, high dynamic range, and low power dissipation. An FM demodulator based on sigma-delta frequency-to-digital conversion decouples dynamic range from power dissipation to achieve a resolution of 41.1µHz in a 50 Hz bandwidth for a 30 kHz signal (2.1 mdeg/s/√Hz) with a maximum input range of 2000 deg/s while consuming 27.6µA at 1.8V. The high performance and low power consumption of this circuit enable the development of high performance, ultra-low-power, frequency-output gyroscopes and other frequency-output MEMS sensors.

A dual slope direct digital converter (DDC) suitable for resistive sensor elements already connected in the form of a Wheatstone bridge is presented here. The proposed DDC accepts the whole bridge as an integral part of a dual slope analog to digital converter and provides a digital value proportional to the input quantity being sensed by the four resistive sensing elements of the bridge. Simulation studies establish the efficacy of the proposed DDC. Maximum error observed in the simulation study was

This paper presents an experimental investigation for the performance of a PV generator using Cassy System environment. Two PV panels were exposed to severe environmental conditions such as high temperature, high humidity, relatively high irradiation and frequently high levels of dust deposition. Each PV panel of 150 W rating was feeding a variable resistive load. The measurement was taken through a conditioning amplifier and Profi-Cassy analog to a digital converter. Cassy System displayed the voltage, the current, the delivered power and the irradiation on-line with the desired frequency of measurement and storage rate. I-V and P-V characteristics were accurately displayed and stored. Cassy environment allows appending the characteristics for the sake of comparison, investigation and research purposes. The obtained results were validated against simulation to show a very good degree of accuracy. Cassy System environment has shown high degree of simplicity and flexibility in programming, to record and display a large number of variables manually and automatically. The measurement system has shown clearly the impact of dust, of high temperature and of the irradiation changes on the PV panel efficiency certifying his candidacy for research and educational purposes.

We introduce a stochastic time-to-digital converter (TDC) that has 180-770fs tunable resolution, less than 0.6LSB INL, and selectable dynamic range offset. Previous arbiter-based TDCs have fine resolution but small dynamic range which is difficult to calibrate. Our approach uses comparators as decision elements to precisely control dynamic range offset.

Intelligent Transportation Systems (ITS) have been developed worldwide and new technologies are naturally being part of them. Meteorological electronic instruments in ITS applications must fulfil with low cost, low power consumption, size saving and wireless communication. The use of quasi-digital sensors and frequency-to-code converters helps to improve those features, but challenges in the measurand-to-code conversion are appearing in this type of systems. The specific case of adapting the output of a sensor for infrared (IR) light detection based on a quasi-digital photo detector is presented in this work. A low relative error of 10% under both indoor and outdoor conditions was determined. The result obtained suggest that this novel proposal may be used to assess the performance in visibilimeters, transmissometers, rain detectors, and current weather instruments used in ITS applications.

A low power interface circuit for multisensory system is presented in this paper. A SAR capacitance-to-digital converter (CDC) and a SAR analog-to-digital converter (ADC) are combined together so that capacitance or voltage from different sensors can be measured by the same circuit and converted to digital signal directly. A dynamic comparator with self-calibration is designed to achieve zero-static power. Bootstrapped switches and bottom-plate sampling are used to reduce the non-idealities of sample/hold circuit. The 11bit converter is designed in 0.18um CMOS process with a core area of 0.1764 mm 2 . It consumes 6.7µW and achieves an energy efficiency of 18.8 fJ/conversion-step as a CDC.

It is known that multiple rotating transformer, as the high precision of state information such as location, velocity, and acceleration, is widely used in the numerical servo control system. The principle of the multiple rotating transformers and its detecting method is firstly detailed, and then the tracking control system with the control core of TMS320F2812 and speed detecting element of multiple rotary transformer is designed. Additional, the interface between multiple rotary transformer and its digital converter as well as software flow chart is described. Finally the man-machine interface is designed. Experiment result shows that all off the hardware and software work well and truly finish appointed function.

A Phase-to-Digital Converter (PDC), — an improved scheme of Time-to-Digital Converter (TDC) —, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

Application of Universal Frequency-to-Digital Converter (UFDC-1) for design of low-cost, smart temperature sensors systems based on quasi-digital sensors is described in the paper. Designed sensors systems have self-adaptation and self-identification abilities. Experimental results have confirmed high metrological performances of designed sensors systems.

An 18-bit analog-to-digital converter has been designed that uses the principle of ovcrsampling rather than the successive-approximation technique of most converters. The design employs a two-stage digital filter/decimator to reduce the sampling rate. Unusual digital filter structures are used to reduce the computation rate to a practical level. Extension to 19 bits and beyond is discussed.

PXI is the expansion of PCI in instrument field. It has formed a rule of mechanism, electric and software which can be applied to the field of testing, measuring and data-sampling. The digital converter module of synchro resolver-to-digital converter converts analog angle signals into digital signals, then connects to computer by PXI. Thus the intelligence of the instrument can be realized. In this paper, the work principle, hardware configuration and software design of synchro resolver-to-digital converter are described.

This paper presents a novel resistance-to-digital converter (RDC) suitable for differential resistive sensors. The proposed RDC provides a digital output linearly proportional to the parameter being sensed by a differential resistive sensor not only for differential resistive sensors possessing linear characteristic but also for sensors possessing inverse characteristic. The proposed RDC is based on the sigma-delta type analog-to-digital converter (Sigma-Delta ADC) principle and hence possesses all the advantages and limitations of a Sigma-Delta ADC. Experimental results on a prototype built and tested gave a worst case error < 0.15 %, establishing the efficacy of the proffered RDC.

This document present a virtual instrument dedicated to modeling the analog - digital converter, for use in e-learning applications.

We report for the first time radiation data on a radiation-hardened high-precision resolver-to-digital converter (RDC). The RDC has a maximum of 16 bits precision, and is manufactured in a total-dose hardened 0.6 /spl mu/m CMOS process. Single-event (SEL) and dose-rate latchup hardening are designed-in using guard rings and DICE latches. Our results show total-dose hardness levels of 1 Mrad(SiO/sub 2/), SEL and dose-rate latchup immunity, and geosynchronous-orbit single-event-upset (SEU) rates of 5/spl times/10/sup -5/ upsets/device/day.

This paper illustrates through the example of a hardened absolute digital converter, one way to meet the accuracy and hardening requirements of the nuclear robotics field. The method consists in performing iterations until a trade-off is found between architecture choices and devices choices, in order to achieve a given hardening level. The system is found to be still functional after 150 kGy. Such a method can be applied to other equipments used in nuclear robotics.