68 results on '"Dill, David"'
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2. Automatic Formal Verification of Block Cipher Implementations
3. A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification
4. Multi-threaded reachability.
5. Chapter 7: Complete Trace Structures: 7.6: Complete Trace Structures as a Lattice.
6. Chapter 7: Complete Trace Structures: 7.5: Examples or Complete Trace Structures.
7. Chapter 7: Complete Trace Structures: 7.3: Complete Trace Structures are a Circuit Algebra.
8. Chapter 7: Complete Trace Structures: 7.2: Complete Trace Structures and Receptiveness.
9. Chapter 6: Infinite Sequences and Infinite Games: 6.5: Decidability of Regular Games.
10. Chapter 6: Infinite Sequences and Infinite Games: 6.3: Regular Languages of Infinite Sequences.
11. Chapter 6: Infinite Sequences and Infinite Games: 6.2: Mathematical Preliminaries: Infinite Sequences.
12. Chapter 5: An Automatic Verifier: 5.5: Example 2: Martin's Distributed Mutual Exclusion Circuit.
13. Chapter 5: An Automatic Verifier: 5.4: Example 1: Tree Arbiter.
14. Chapter 5: An Automatic Verifier: 5.2: Descriptions and Specifications.
15. Chapter 4: Verification: 4.5: Examples.
16. Chapter 4: Verification: 4.3: Conformation Equivalence and Simplifications.
17. Chapter 3: Prefix-closed Trace Structures: 3.3: Prefix-Closed Trace Structures.
18. Chapter 3: Prefix-closed Trace Structures: 3.4: Examples.
19. Chapter 2: Circuit Structure: 2.6: Structural Completeness.
20. Chapter 1: Introduction: 1.3: Background and Related Work.
21. Chapter 1: Introduction: 1.1: Introduction.
22. A simple method for extracting models for protocol code.
23. Sequential circuit verification using symbolic model checking.
24. Architecture validation for processors.
25. Approximate algorithms for time separation of events.
26. Efficient validity checking for processor verification.
27. Modeling hierarchical combinational circuits.
28. Unifying synchronous/asynchronous state machine synthesis.
29. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits.
30. Validation with guided search of the state space.
31. Approximate reachability with BDDs using overlapping projections.
32. New techniques for efficient verification with implicitly conjoined BDDs.
33. Reducing BDD size by exploiting functional dependencies.
34. Automatic technology mapping for generalized fundamental-mode asynchronous designs.
35. Automatic Synthesis of Extended Burst-Mode Circuits: Part II (Automatic Synthesis).
36. Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-Free...).
37. An Executable Specification and Verifier for Relaxed Memory Order.
38. Chapter 7: Complete Trace Structures: 7.7: Practical Considerations.
39. Chapter 5: An Automatic Verifier: 5.3: Conformation Checking.
40. Chapter 4: Verification: 4.7: Lattice Properties.
41. Chapter 2: Circuit Structure: 2.5: A Circuit Algebra of Circuit Structures.
42. Chapter 2: Circuit Structure: 2.4: A Representation of Circuit Structures.
43. Chapter 2: Circuit Structure: 2.3: Circuit Algebra.
44. Chapter 2: Circuit Structure: 2.1: Introduction.
45. Chapter 1: Introduction: 1.5: Overview of the Thesis.
46. Chapter 1: Introduction: 1.2: Verification Issues.
47. Chapter 8: Conclusion: 8.1: Summary.
48. Chapter 8: Conclusion: 8.2: Future Work.
49. Chapter 7: Complete Trace Structures: 7.1: Introduction.
50. Chapter 6: Infinite Sequences and Infinite Games: 6.4: Infinite Games.
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