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Refined products pipeline system is one of the most economic and effective transportation modes. Many scholars have conducted some research on the oil batch scheduling optimization of refined products pipeline. However, solving the model of a large refined products pipeline scheduling problem usually costs a long time. It also does not involve in automatic scheduling plan developing. In this paper, considering the batch tracking, flow rate constraints, hydraulic constraints and taking the minimum volume deviation between demand volume of each station and the actual unloading volume as the objective function, a mixed integer nonlinear programming (MINLP) model has been established for a large single-source refined products pipeline with multiple output stations. A heuristic algorithm is used to solve this model. The real-world pipeline from Mao Ming to Da Li, part of the Southwest China pipeline network, is taken as the study case. A long term scheduling model for this pipeline is established and solved in this paper. A complete detailed scheduling plan in the whole time horizon is given automatically. The average computing time of the model is 31.70s and the results are in accordance with the process and situation in field. The research achievement is significant and helpful to develop scheduling plan for a large single-source pipeline with multiple output stations.

In this paper, we present a shadow generation method based on our previous tricolor linear attention shadow model. Compared with shadow generation methods in Graphics or based on matting and compositing shadow generation, our method does not need complex calculations or any matting operation, but only to calculate the pixel values of generated shadow on the basis of original image pixel information and tricolor values linear attenuation of shadow. This physically-based shadow generation method enhances the visual effects of shadow generation. A series of experimental results validate this method.

In this paper, an embedded 3.3 V 2 Mb SIBE-based flash memory is introduced. Some novel circuit technologies, such as the DINOR memory array architecture, the row decoder with high performance negative voltage switch and the sector decoder, are described in detail. By introducing a negative logic level circuit in the sector decoder, the maximum high voltage stress is reduced to 8 V. The simulated and tested results show that the SIBE-based Flash memory has low program power, high access speed and high performance.