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This paper focus on the problem that advanced smart contract language (ASCL) are hard to put into practice due to the lack of an effective conversion method from ASCL contract to executable smart contract programs. Aiming at this problem, we take SPESC as example to explore how to design conversion rules from the contract in it to the target programming language in Solidity. These rules provide an approach to convert the definition of SPESC contracting parties into party-contracts on target language, as well as to produce SPESC contract terms into main-contract on target language. Moreover, the proposed framework specifies not only program architecture and storage structure on general smart-contract layer, but also important mechanisms, including personnel management, timing control, exception handling, etc., which can assist programmers to write smart contract programs. Furthermore, taking four SPESC contracts as testing objects, we provide the whole process of converting from SPESC contracts to Solidity programs by SPESC-Translator, and verify the efficiency and security of the conversion process, including coding, deploying, running, and testing through Ethereum. The instance results show that the proposed rules can simplify the writing of smart contracts, standardize program structure, and help programmers to verify the correctness of contract programs.

we propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less error-prone. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. If the wafer map matches one of the known defect patterns, then RCA can be done efficiently.

This study aims to exploit an integrated-circuit (IC) testing model based on a statistical simulation method to evaluate the test yield and quality of IC products. Using normal probability distributions of product properties, we digitally analyzed IC yield and quality, introduced testing threshold and guardband, and assessed various parameters’ influence on outcomes. Because future manufacturing speed is unpredictable, we used current manufacturing technology and existing-product electrical properties to estimate future product-distribution trends. Since the progress of developmental improvements for testing technologies has been slow, it has become a greater challenge for a supplier to determine the use of existing instruments and tools to achieve quality products with near-zero defects. To improve product quality, a new scheme of Multiple tests has been proposed. Moreover, we used a set of parameters from the International Technology Roadmap for Semiconductors (ITRS) to demonstrate the proposed Multiple testing, and to show that the test yield can be improved while attaining the desired quality.

Premature infants or neonates in need of advanced clinical care must be transported to specialized hospitals. Past studies have examined vibrations experienced by patients during transport; however, multiple confounding factors limit the utility of on-road data. Hence, the development of a standardized test environment is warranted. The overall purpose of this project is to characterize vibrations during neonatal patient transport and develop mitigation strategies to reduce exposure. This paper focusses on the development of a laboratory test environment and procedure that enables studying the equipment vibration in a comprehensive and repeatable manner. For the first time, a complete neonatal patient transport system, including a stretcher, has been mounted on an industrial shaker. Results largely validate the system's ability to simulate on-road vibrations with high repeatability.

Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

We present (i) a novel, thermally stable Atomic Layer Deposition (ALD) high-k dielectric stack that, for the first time, has the potential to meet all gate stack requirements for both n- and p-channel Ge FETs, (ii) record low contact resistivity for n-Ge/metal contacts using an implant-free contact scheme with successful implementation into a single nanowire (NW) Ge nFET baseline, (iii) single NW Ge pFETs with short-channel effect (SCE) immunity down to 24 nm physical gate length, of which electrical data show excellent agreement with calibrated models and (iv) demonstration of Ge-channel vertically stacked lateral NW FETs using a 300 mm VLSI compatible platform.

How to efficiently place virtual machines is an important issue in the cloud data center. Virtual machine placement method based on traditional heuristic algorithm costs long time to reach an optimal allocation so that it is difficult to meet the real production environment. To solve this problem, this paper proposes a virtual machine placement method based on improved simulated annealing algorithm (ISA). Firstly, resource utilization model of servers and dynamic placement model for virtual machines are introduced. Secondly, two threshold values and an optimized annealing process are presented in the ISA. Finally, the ISA-based allocation weight vector is computed. Experimental results show that the method determines virtual machine placement in a short time span, achieves load balance and improves resource utilization rate in the cloud data center, as well as reduces the number of active servers.

This paper introduces a 4-dimensional chaotic map, consisting of sine, and cosine functions. Using this map and a generalized synchronization (GCS) theorem designs an 8-dimensional GCS system. The GCS system is used to design a chaotic pseudorandom number generator (CPRNG). Using the FIPS 140-2 test suit/generalized FIPS 140-2 test suit tests the randomness of three 1000-key streams consisting of 20000bits generated by the CPRNG, the RC4 algorithm and the ZUC algorithm, respectively. The results show that there are100%/98.9%, 99.9%/98.8%, 100%/97.9% key streams passing the tests, respectively. The analysis of the keys sensitivity suggests that there are no significant correlations between the key stream and the perturbed key streams. The key space of the CPRNGis larger than 2 1195. The CPGNG with an avalanche effect encryption scheme is used to encrypt an RGB image. The numerical calculations demonstrate that the CPRNG can generate the avalanche effects which are similar to those generated by ideal CPRNGs.

An UHF-band circularly polarized microstrip antenna with two Asymmetric Circular slots is designed. The square microstrip patch has a single-feed configuration and two Asymmetric Circular slots. The antenna can be adopted to achieve the relatively compact circularly polarized microstrip antenna. Two Asymmetric Circular slots with different sizes along the diagonal directions are notched in the square microstrip patch to reduce the size of the microstrip antenna, and to produce circularly polarized radiation at the same time. Unbalanced patch along the diagonal directions in slotted areas is the root cause of the circularly polarized radiation. The antenna has a 6.0MHz 3-dB axial-ratio bandwidth as well as 20MHz impedance bandwidth, covers the UHF-RFID band from 920.5MHz to 924.5MHz.

Increasing importance of FlexRay systems in automotive domain inspires unceasing comparative researches. One primary issue among researches is to verify the reliability of FlexRay systems either from protocol aspect or from system design aspect. However, for more precisely addressing the FlexRay system reliability issue, we require a more generic analysis that simultaneously considers the network topology, clock sync between FlexRay ECUs and the ECU fault-tolerance. To fulfill this requirement, in this paper we first apply a well-known reliability model, Dynamic Fault Tree (DFT), to model the reliability of FlexRay systems with various network topologies, and then employ the Markov Chain (MC) to model the reliability of clock sync in terms of the number of sync ECUs. Furthermore, various fault-tolerant techniques for ECUs protection are also modeled by MC. The adopted two reliability models, DFT and MC, are integrated to form a mixed DFT to assess the FlexRay system reliability more accurately. Through a FlexRay steer-by-wire case study, we demonstrate the influence of different topologies, different ECU fault-tolerance and various number of sync ECUs on the reliability of FlexRay steer-by-wire system.

Parallel plate ionization chambers with segmented strips or pixels are developed for proton beam monitoring and dose measurement. 256 channels of readout electronics together with high voltage power supplier, FPGA and USB are built on a single PCB and readout by LABVIEW based DAQ system. With replaceable resistors, sensitivity of each channel varies from 1 ADC / 1 nA to 1 ADC / 5 pA to handle large dynamical range in proton therapy. Chambers are tested with 100,200 and 394 MeV proton beams with narrow beam widths. Beam profiles obtained by strip and by pad chambers are compared. Depth dose distributions of protons in water are obtained with 100 and 200 MeV proton beams. Results from the GEANT4 simulation reproduce measurement reasonably.

Paralleling square unit capacitors have been commonly used for Switched-Capacitor circuits to achieve higher accurate capacitor ratio. However, the capacitor ratio may be shifted due to the wire interconnection of these unit capacitors. The small capacitor ratio shift may cause a significant yield drop. The ratio shift can be reduced by using extra circuitry to achieve parasitic insensitive design. This study presents a simple a layout modification to alleviate the ratio shift, thus enhancing yield, without requiring extra circuitry.

A high speed and low power CMOS current-mode circuit design is proposed for generating an S-shape correction curve. We divide the correction curve into three segments to reduce the polynomial order for curve fitting. We assemble three simple current-mode circuits to construct an S-shape correction curve generator. The circuit consists of only 16 transistors and 3 current sources. The −3dB bandwidth and the maximum power dissipation are 285 MHz and 2.97 mW, respectively. The input

An electrical model of the 104 MHz radio frequency quadrupole (RFQ) accelerator at Peking University is introduced for RF design, based on which every crucial geometrical parameter is swept and selected carefully to improve the RF properties of the RFQ such as the intrinsic quality factor and shunt impedance for reducing its power consumption. Moreover, flatness tuning of the inter-electrodes voltage is investigated in principle. Also, a magnetic coupling loop is designed for power feeding of the RFQ cavity from transmitter. Relevant numerical simulations are performed using 3D electromagnetic field program CST Microwave Studio (MWS).

An innovative design of 16-channel front-end electronics for ionization chamber in monitoring proton beam profile has been developed to feature simplicity, low cost, durability, and reliability without compromising its performances. All the parts are available off the shelf. The front-end electronics board is powered by USB connection, through which the data are transferred to the host computer for storage and further online analysis. The system has been studied with Geant4 MC [1] and tested with both electron and proton beams.

The increasing importance of FlexRay systems in automotive domain inspires unceasing relative researches. One primary issue among researches is to verify the robustness of FlexRay systems either from protocol aspect or from system design aspect. However, research rarely addresses the issue that network topology selection will also cause difference in robustness. In this paper, we will illustrate how to model the robustness under various network topology adoptions by a well-known technology, fault tree analysis (FTA). Quantitative and qualitative analysis results can show the potential and suitability of FTA for modeling FlexRay systems' robustness.

Navigation of unmanned underwater vehicle (UUVs) in unstructured environments without long baseline transponders is a challenging problem due to the lack of predefined sea floor landmarks. This study proposes a real time sea floor mapping method using sidescan sonar on UUVs. The mapping system combines the motion information and the observation model of the sidescan sonar. The observation process firstly detects environmental features and then localizes the feature positions relative to the UUV. The landmark localization procedure considers the working principle of sidescan sonar and the acoustic velocity in sea water to localize the landmark and calculate the sidescan sonar footprint region. An occupancy grid mapping algorithm is then used to map the sea floor combining the uncertainties of UUV's motion and measurement errors from the observations. This procedure was implemented on an UUV to verify its landmark detection capability. Experimental results conducted on sandy seabed with concrete targets are demonstrated.

FlexRay, as a communication protocol for automotive control systems, is developed to fulfill the increasing demand on the electronic control units for implementing systems with higher safety and more comfort. Fault-tolerant feature is especially highlighted in the FlexRay protocol such that the FlexRay systems can be robust enough for applying to the safety-critical applications. In this work, we investigate the fault-tolerant mechanisms adopted in the FlexRay protocol, and propose an effective verification flow to justify the FlexRay communication robustness. The goal of the proposed flow is to ensure that the communication robustness can achieve the demanded safety integrity level (SIL) defined in IEC 61508 norm. Through a case study, the feasibility of the verification flow is demonstrated.

FlexRay, as a communication protocol for automotive control systems, is developed to fulfill the increasing demand on the electronic control units for implementing systems with higher safety and more comfort. Fault-tolerant feature is especially highlighted in the FlexRay protocol such that it can be robust enough to apply for the safety-critical automotive applications. In this work-in-progress report, a verification strategy of the fault-tolerant mechanisms (FTMs) adopted in the FlexRay protocol is introduced. Our goal is to assess the effectiveness of FTMs to common interferences including EMI, SEU and crosstalk. We will also build up a simplified steer-by-wire system for observing its abnormal behaviors when the FTMs cannot overcome the interferences. All the investigations provide a transparent figure to the robustness of the FlexRay systems.

Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as ?index?, the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations.

Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes analytical models for predicting the cache contention and throughput of heavily multithreaded architectures such as Sun Microsystems' Niagara. First, it proposes a novel probabilistic model to accurately predict the number of extra cache misses due to cache contention for significantly larger numbers of threads than possible with prior analytical cache contention models. Then it presents a Markov chain model for analytically estimating the throughput of multicore, fine-grained multithreaded architectures. The Markov model uses the number of stalled threads as the states and calculates transition probabilities based upon the rates and latencies of events stalling a thread. By modeling the overlapping of the stalls among threads and taking account of cache contention our models accurately predict system throughput obtained from a cycle-accurate performance simulator with an average error of 7.9%. We also demonstrate the application of our model to a design problem—optimizing the design of fine-grained multithreaded chip multiprocessors for application-specific workloads—yielding the same result as detailed simulations 65 times faster. Moreover, this paper shows that our models accurately predict cache contention and throughput trends across varying workloads on real hardware—a Sun Fire T1000 server.

As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical models have been employed to rapidly search for higher performance designs, and can provide insights that detailed simulators may not. This paper proposes techniques to predict the impact of pending cache hits, hardware prefetching, and realistic miss status holding register (MSHR) resources on superscalar performance in the presence of long latency memory systems when employing hybrid analytical models that apply instruction trace analysis. Pending cache hits are secondary references to a cache block for which a request has already been initiated but has not yet completed. We find pending hits resulting from spatial locality and the fine-grained selection of instruction profile window blocks used for analysis both have non-negligible influences on the accuracy of hybrid analytical models and subsequently propose techniques to account for their effects. We then introduce techniques to estimate the performance impact of data prefetching by modeling the timeliness of prefetches and to account for a limited number of MSHRs by restricting the size of profile window blocks. As with earlier hybrid analytical models, our approach is roughly two orders of magnitude faster than detailed simulations. When modeling pending hits for a processor with unlimited outstanding misses we improve the accuracy of our baseline by a factor of 3.9, decreasing average error from 39.7% to 10.3%. When modeling a processor with data prefetching, a limited number of MSHRs, or both, the techniques result in an average error of 13.8%, 9.5% and 17.8%, respectively.

As a kind of service economy, the financial industry could play an important role in releasing China's unemployment pressure and promoting economic growth; especially it could have a strong active employment effect in the economic development. This paper uses the financial innovation theory to analyze the employment effect of the financial industry in China, and then focuses on analyzing the direct employment effect of the financial industry. At last, it puts out some suggestions on innovational policy choices for developing of the financial industry in order to improve its employment effect fully.

Software aging refers to the phenomenon that long-running software shows signs of increasing failing rate, overmuch resource usage, and performance degradation. Software rejuvenation is a proactive approach to dealing with this problem. However, commonly used rejuvenation methods involve a relatively larger overhead. An alternative is to reduce the severity of software aging by online adjusting the settings of related parameters of the system. In this paper, we conduct controlled experiments to analyze severity of software aging under different settings of related parameters. Based on the experimental data, a metric is defined to measure the severity of software aging. A multiple-input and multiple-output (MIMO) model is then constructed to formulate the relationship between severity of software aging and related parameter settings. The proposed MIMO model gives us a way to control the severity of software aging at runtime.

The term supply chain management (SCM) has risen to prominence in the past few years. SCM extends the concept of functional integration beyond a firm to all the firms in the supply chain. The individual members of a supply chain help each other improve the competitiveness of the supply chain, which should improve competitiveness for all supply chain members. This study attempted to contribute to the body of knowledge of marketing and logistics by empirically investigating the relationship between the customer demand and SCM. An integrative mathematical model was developed and specific relationship was founded about the customer demand and SCM and how it can enhance business performance of the individual firms in a supply chain.

The system design and implementation of Sigma-Delta modulator of fractional-N phase locked loop in local positioning systems are presented. The behavioral model of the complete SigmaDelta-fractional-N PLL was developed that provides phase noise and RMS phase jitter estimation and optimization as function of the unity gain frequency. It is shown that the level of RMS phase jitter obtained with a 3rd order SigmaDelta fractional - N PLL is comparable to the levels of RMS phase jitter obtained with DDS realizations. However, SigmaDelta fractional-N PLL synthesizers present lower power consumption, compact design and better frequency ramp linearity than DDS realizations for linear FM systems. Digital and analog co-simulations and implementation of SigmaDelta-modulator and pre-emphasis IIR filter design were carried out. The measurement results of the SigmaDelta-modulator using a linear FM sweep were verified on Xilinix-FPGA platform.

Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper presents an efficient BISR scheme for multiport RAMs (MPRAMs). The BISR scheme has a defect-location module (DLM) executing a defect-location algorithm to locate inter-port defects. This enhances the fault-location capability of the applied test algorithm with only a few amount of cost of testing time. A built-in redundancy analyzer (BIRA) executing a proposed redundancy analysis algorithm is also proposed to allocate two-dimension redundancy of MPRAMs. Experimental results show that if a faulty MPRAM has 20% inter-port faults, the DLM can boost the increment of repair rate from 8.4% to 14.4% for different redundancy configurations. The area cost of the BIRA and DLM is small, it is only about 1% for a 4096 times 128-bit MPRAM with 1 spare row and 1 spare IO.

We demonstrate the use of an optical equalizer to allow a 42.7-Gbaud (85.4-Gb/s) NRZ-DQPSK signal to tolerate the narrow optical filtering required in high-spectral-efficiency systems. The equalizer passbands are repetitive, enabling equalization of multiple channels.

Recently, a kind of phenomenon known as software aging has been reported in many studies, characterized by progressive performance degradation or abrupt crash/hang. Software aging is directly related to resources usage. In this paper, we set up an experimental platform with multi-clients, collect data on system resource usage on Web server and log data on performance on client. It is observed that there is performance degradation while the amount of available memory remains constant. Results show that there is significant correlation between response time and buffer. Finally, we calculate the largest Lyapunov exponent of time series of average load, and results show that software aging process is chaotic

The random-like filling strategy pursuing high compression for scan test introduces large test power. To pursue high compression in conjunction with reducing test power for multiple scan chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a Multilayer Data Copy (MDC) scheme for test compression as well as test power reduction for multiple scan designs. The scheme utilizes a buffer, which supports fast load using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied ATPG-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with little area design overhead.

This paper presents a reconfigurable built-in self-repair (ReBISR) scheme for multiple repairable RAM cores with different sizes and redundancy organizations (i.e., spare rows/spare columns or spare rows/spare IOs). We also propose an efficient built-in redundancy-analysis (BIRA) algorithm for allocating redundancies for the ReBISR scheme. A reconfigurable BIRA (ReBIRA) circuit is realized to perform the proposed BIRA algorithm for the ReBISR scheme. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). The area cost of the reconfigurable BIRA is very small, e.g., the area cost is only about 1.5% if 512times4times256 design parameters and four memory instances (64times2times32, 128times2times64, 256times4times128, and 512times4times256) are considered. Also, the ratio of the redundancy analysis time to the test time is very small, e.g., the ratio for a 512times4times256-bit memory tested by a March-14N algorithm with solid data backgrounds is only about 0.25%

A planar lightwave circuit with a length-imbalanced Mach-Zehnder interferometer and an arrayed waveguide grating radiating into free-space generates nonlinearly spatially dispersed light. This arrangement is advantageous for mitigating mirror edge effect in MEMS-based components.

IPv6 protocol which would replace IPv4 in the near future is a major boost to network technology as it has many inherent good qualities that IPv4 lacks. We seek to analyze some features of the IPv6 network communication. To understand more on the co-existence technology between IPv4 and IPv6, tunneling and dual stack technology were configured in simulation. Thus 6 to 4 tunnel network and multi-tier dual stack network were analyzed and studied through simulation. The analysis of these network behaviors is presented through generated graphs that show the IPv6 traffic patterns or performance aspects.

The supply of high quality electrical energy in power systems requires access to a synchronized phasor that is measured at various locations via a phase measurement unit (PMU). These data are then tagged with timestamps, provided by a Global Positioning System (GPS), and then sent to a control unit. The existing methods place demanding constraints on the computing resources; hence, a new method of extracting synchronized phasors is proposed to address this issue. The new method combines a multirate phase locked loop (MPLL), a real-time positive sequence detector, and a GPS common time-stamp unit. The MPLL is based on a PLL architecture that incorporates frequency adaptation intrinsically. The MPLL constitutes a multirate sample rate system that relaxes the implementation of a front-end analog anti-aliasing filter. Furthermore, a digital bandpass filter is included to enhance the performance of the MPLL under severe line disturbance conditions. An automatic gain control (AGC) prevents any variations of amplitude in the input signals from affecting the PMU

Synchronization is of concern in AC power systems. Existing synchronization algorithms are hardware intensive. A single phase synchronization scheme referred to as a multi-rate phase locked loop (MPLL) has been reported. The stability of the MPLL is influenced by amplitude variations. An amplitude estimation module based on a fast Fourier transform (FFT) algorithm and an automatic gain control (AGC) are employed to decouple amplitude variations from phase variations. The implementation of the FFT-based amplitude-estimator is complex and hardware intensive. A peak detector module that utilizes only two multiplexers and one comparator is proposed to replace the FFT-based amplitude-estimator. A real-time positive sequence detector is also combined with the MPLL in order to allow process of the three-phase signals. The overall system is implemented and compared for both FFT-based and peak detector approaches and indicates a 60 dB immunity to impulse noise and harmonic contamination and a 20 dB dynamic range

This paper describes the design and implementation of a DSP-based fully digital-controlled single-phase on-line uninterruptible power supply (UPS) system. All the control functions for an on-line UPS, which includes power-on start-up control, input stage power factor control, battery charging and boosting control, output stage AC voltage regulation, and shutdown control, are realized by using a single-chip DSP controller. A multiple rate digital controller generates all the PWM control signals for the power stage by using a set of detected feedback signals. Software current control scheme with nonlinear pulsewidth compensation has been developed to eliminate the nonlinearity caused by the dead-lock protected PWM converters. A nonlinear digital control scheme with lower switching frequency has been developed for the power factor control of the AC-DC converter. Experimental results have been given to verify the proposed digital control scheme. The constructed DSP-controlled UPS system can achieve fast dynamic response for nonlinear loads and high power factor under various loading conditions.

An on-chip active balun with gain and phase mismatch within 0.5 dB and 1 degree, respectively, integrated with a gain controllability feature, is presented. Applicable for direct conversion receiver circuits, the balun has been designed to operate in the 5-6 GHz range with a bandwidth of 400 MHz. With an output P1dB of -14.4 dBm, it is capable of being used as an independent amplifier in addition to acting as an active balun.

An on-chip active balun with good gain and phase mismatch performance of within 0.5 dB and 1 degree, respectively, is presented in this paper. Applicable for direct conversion receiver circuits, the presented balun features reconfigurability in the form of controllable gain, designed to operate in the 5-6 GHz range with a bandwidth of 400 MHz. With good linearity, input/output matching and gain and with improvement in noise performance, the proposed active balun circuit could effectively be used as the first stage of an RF front end replacing the LNA.

In this paper, we propose a BIST scheme for the digital-to-analog converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. An 8-bit DAC BIST circuit is designed for demonstration.

The crosstalk fault effects in deep sub-micron VLSI, namely, glitches and the crosstalk-induced delay, are investigated. The origin of their occurrence, relationship and importance in circuit operation are elucidated. It is shown that the crosstalk-induced delay is only superposition of the induced glitch with the original signal delay on the affected victim line; and crosstalk-induced delay is more important in affecting the circuit performance, and should be considered in more details for testing. A scheme which is to detect both types of faults in a unified way by just detecting glitches is proposed and studied, considering the manufacture process variation. In this way, detection of crosstalk-induced faults becomes much easier.