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In this paper, we consider the decode-and-forward (DF) relay system in millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems, and propose a hybrid beamforming design method for the mixed structure, which contains the fully-connected and sub-connected structures. To satisfy constant-modulus and block-diagonalization (BD) constraints, the analog beamforming is designed by the idea of sorted successive interference cancellation (SSIC). More specifically, the proposed method first sorts the capacities of different analog sub-channels in descending order, and then designs the analog beamforming serially according to the order of the capacities. To efficiently mitigate the inner-user and inter-user interference, we propose a modified baseband BD technology to reduce the information loss in digital beamforming design, thereby improving the system capacity. In addition, the proposed hybrid beamforming algorithm is designed by considering both uniform linear arrays (ULAs) and uniform planar arrays (UPAs). Simulation results demonstrate that the proposed hybrid beamforming design scheme can obtain good performance in terms of the achievable sum-rate and power efficiency in ULAs and UPAs.

This paper presents two designs of a capacitively-coupled chopper instrumentation amplifier (CCIA) successfully implemented in 28 nm CMOS for biopotential sensing applications. The first design is a compact CCIA using offset-blocking for chopping ripple reduction, DC servo loop (DSL) for electrode offset ( $V_{\mathrm {EOS}}$ ) suppression, and a high pass filter (HPF) for handling common-mode (CM) artifacts. An inverter-based self-biased input stage is used for noise and power efficiency. The two gain stages of the CCIA achieve a low-frequency open-loop gain >80 dB. Realized in an area of 0.05 mm2, the CCIA handles $V_{\mathrm {EOS}}$ up to 50 mV and tolerates CM artifacts up to $1.5~V_{\mathrm {pp}}$ . The CCIA achieves a mid-band gain of 39.5 dB with a 1 kHz bandwidth by consuming $1~\mu \text{W}$ . The integrated input-referred noise (IRN) over 200 Hz bandwidth is $2.15~\mu V_{\mathrm {rms}}$ . The second design presents a dual-channel CCIA (DCCIA) using an orthogonal frequency chopping for multi-sensor array applications. An inverter-based input stage is used for noise efficiency. The measured results show that the DCCIA achieves a low-frequency gain of 39.5 dB with a 3-dB bandwidth up to 1 kHz by consuming $0.71~\mu \text{W}$ per channel. The measured noise density is 136 nV/ $\surd $ Hz with an integrated noise of $2.67~\mu V_{\mathrm {rms}}$ over 200 Hz bandwidth. The DCCIA suppresses $V_{\mathrm {EOS}}$ up to 50 mV using the DSL. Realized in a compact area of 0.04 mm2 per channel, an excellent gain matching error of 0.29% is achieved with the crosstalk higher than 58 dB between the channels. This work is a measured report on the instrumentation amplifier using, to the best of the authors’ knowledge, one of the smallest CMOS process nodes.

The GaN-based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter with full-line-cycle zero voltage switching (ZVS) is a promising candidate for high-efficiency front-end rectifiers. However, the input current can be degraded by line-cycle current distortion and ac line zero-crossing current spikes, and maintaining reliable ZVS control is difficult in noise-susceptible high-frequency environments. In this paper, a detailed analysis of the current distortion issues in a GaN-based CRM totem-pole PFC with digital ZVS control is provided, and effective approaches are proposed to mitigate different kinds of current distortion and ensure stable ZVS control under high-frequency operation. The proposed solutions have the advantages of straightforward implementation and do not increase the control complexity. The current distortion issues are demonstrated in two GaN-based CRM totem-pole PFC prototypes, a 1.5 kW PFC for data centers and a 100 W PFC in a 6.78 MHz wireless charging power supply for consumer electronics. The proposed methods are experimentally verified with effective mitigation of the current distortion and improvement of the converter power efficiency.

Targeting the more recently adopted low-power memories for data-logging operation in IoT nodes, this paper presents a simple reconfigurable dual-branch cross-coupled charge pump (CP) topology in which clock amplitude scaling and modulation of the number of stages are exploited to improve power efficiency and/or change the output voltage without degrading speed performance. The proposed solution allows a reduction of the power conversion losses, maintaining speed, maximum output voltage and silicon area unaltered as compared to the conventional charge pump. Post-layout simulation results confirm the effectiveness of the proposed topology which can be adapted to any other kind of linear charge pump.

In this work, a new control methodology is proposed for Type -IV wind energy conversion system (WECS) using a self-recurrent wavelet neural network (SRWNN) control with a Vienna rectifier as the machine side converter (MSC). A SRWNN combines excellent dynamic properties of recurrent neural networks and the fast convergence speed of wavelet neural network. Hidden neurons of SRWNN contains local self-feedback loops, which provide the memory feature and the necessary information of past values of the signals, allowing it to track maximum power from WECS under varying wind speeds. The Vienna rectifier allows unity power factor operation to increase electrical efficiency. Frame angle-controlled wavelet modulation is proposed for the grid side converter (GSC). Wavelet modulated inverter produces output voltage fundamental components with higher magnitudes than those obtained from the pulse width modulated inverters. The non-linear load compensation and power quality enhancement are achieved by executing frame angle control for WM inverter. The overall system is modeled, and performance is verified in MATLAB Simulink. The hardware prototype is developed, and the switching pulses for the rectifier and inverter are generated using dSPACE1104 controller. The results prove that the system provides low harmonic content and high magnitude of the fundamental current component at the machine and grid sides and ensures maximum power operation at various wind speeds.

Convolutional neural networks (CNNs) based deep learning algorithms require high data flow and computational intensity. For real-time industrial applications, they need to overcome challenges such as high data bandwidth requirement and power consumption on hardware platforms. In this work, we have analyzed in detail the data dependency in the CNN accelerator and propose specific pipelined operations and data organized manner to design a high throughput CNN accelerator on FPGA. Besides, we have optimized the kernel operations to obtain a high power efficiency. The proposed CNN accelerator supports image classification and real-time object detection with high accuracy. The evaluation results show that our CNN-based FPGA accelerator can achieve 740 Giga operations per second (GOPS) at 200 MHz with kernel power of 12.2 watts on Intel Arria 10 FPGA. For object detection tasks, our system can achieve 105 fps with 56.5 mAP or 25 fps with 73.6 mAP on VOC dataset. Since we use the mixed fixed-point data representation, the detection accuracy is comparable with the GPU-based YOLO V2 framework. The power efficiency of our system is 3.3× better than Titan X GPU and 418× better than Intel E5-2620 V4 CPU.

A new solution for an ultra-low-voltage, ultra-low-power operational transconductance amplifier (OTA) is presented in the paper. The design exploits a three-stage structure with a Reversed Miller Compensation Scheme, where the input stage is based on a non-tailed bulk-driven differential pair. Optimization of the structure for very low supply voltage is discussed. The resulting amplifier outperforms other ultra-low-voltage OTAs in terms of a DC voltage gain and power efficiency, expressed by standard figures of merit. Experimental verification using a $0.18~\mu \text{m}$ CMOS technology, with supply voltage of 0.3-V, showed a dissipation power of 13 nW, a DC voltage gain of 98 dB, a gain-bandwidth product of 3.1 kHz and an average slew-rate of 9.1 V/ms at 30 pF load capacitance. The experimental results agree well with simulations.

Modern GPUs employ thousands of cores, yielding higher performance but also higher power consumption. To meet performance targets while staying within a reasonable power budget, designers have to make these execution cores increasingly more power efficient. One way to increase their power efficiency is to employ power-efficient adders. In this paper, we observe that consecutive arithmetic computations from the same code location are highly correlated and propose ST2 GPU, a GPU architecture that uses history-based speculative adders that produce guaranteed correct results while saving 70% of the nominal adder power. We estimate that ST2 GPU saves 21% of the GPU chip energy with practically no performance and area overheads.

Mobile edge computing (MEC) is a key enabling technology for supporting high-speed and low latency services in the fifth generation (5G) and beyond networks. MEC paradigm moves computational resources from centralized cloud servers towards the edge of the network, nearer to the users. However, edge computation resources increase the power consumption of the network. Moreover, the non-uniform traffic load on the edge servers causes resources to be underutilized and decrease the system's power efficiency. To achieve the green networking concept encouraged in 5G and beyond networks, unused MEC resources should be switched to sleep mode to reduce the power consumption. The policy controlling sleep/active switching needs should optimize the power consumption and maintain an acceptable quality of service. The control policy should also eliminate frequent mode switches that cause system instability and degrade the system performance. This paper introduces a dual-threshold switching control to reduce power consumption and provide system stability. We also propose using the gaining and sharing knowledge (GSK) optimization algorithm for resource optimization and determining the optimum thresholds to be used by the system. Results showed that dual-threshold switching successfully reduced the power consumed in a single time slot by more than 10% per MEC server. Also, dual-threshold control displayed more stability compared to the single threshold control.

In this study, we show that the effect of the modification on Karthaus-Fischer voltage multipliers for single band GSM RF energy harvesters. To be able to show that, we simulated both circuits for different conditions while assuming the load is purely resistive. Simulation results show that the Karthaus-Fischer voltage multiplier performs slightly better than the modified one in power efficiency but performs remarkably worse in current loading especially under low voltage and high output impedance conditions.

Resonant inductive coupling wireless power transfer (RIC-WPT) systems with multiple transmitters and multiple receivers often suffer from cross-interference among transmitters as well as among receivers. The cross-interference causes the fluctuation of the output power of the receiver and hard switching of the inverter on the transmitter. To avoid the cross-interference, controlling the amplitude and the phase of each transmitter current is an effective method. Therefore, this paper proposes a multiple-transmitter that can compensate for the cross-interference influence by implementing two controls. First, adopting the phase-shift control on the full-bridge inverter, the current amplitude is controlled to be constant. Second, applying the reactance control, each phase of the current is controlled to be in phase. In addition to the above operations, especially under a high-frequency operation, zero-voltage switching (ZVS) at a fixed operating frequency is essential for improving the power efficiency while not exceeding an allowable narrow bandwidth. Thus, the reactance control also works to ensure ZVS in all load conditions without adjusting the frequency. The RIC-WPT prototype with two transmitters and a single receiver is built to verify that the proposed multiple-transmitter can compensate for the cross-interference influence while achieving ZVS in different load conditions at a fixed operating frequency.

This paper presents a dual-path hybrid Dickson (DPHD) converter to provide single-step large-ratio voltage conversions with high power efficiencies. It systematically utilizes a hybrid structure with a N:1 SC network and an inductor to enlarge the duty ratio and reduce the voltage stress of power switches. The hybrid dual-path structure further lowers the required inductor current for a given output current, thereby significantly decreasing the inductor conduction loss and improving the capability of delivering high output current. A 7:1 DPHD converter prototype with 25V silicon MOSFETs was implemented to support conversions from a wide input range of 36 – 65V to an output of 1 – 2V with the maximum load of 30A. The converter achieves a high peak power efficiency of 92.7% under 48V-to-2V conversion and 250kHz. The power density of the converter is 451W/in3 that is better than other prior hybrid converters.

The continued expansion of the global electric vehicle fleet is accompanied by an unprecedented demand for high power density electric traction motors. With the ambitious U.S. DRIVE 2025 target of 50 kW/L power density and an equally aggressive cost reduction goal, innovative approaches have to be utilized in terms of both the design and manufacturing of electric traction motors. In this paper, six motor options are compared and the best design is picked for each option to investigate the drive and excitation requirements and the weighted power efficiency over multiple load points, with necessary mechanical stress and demagnetization checks. State-of-the-art winding technologies, including high slot fill die compressed windings and hairpin windings, and rotors both with permanent magnet (PM) and PM-free are incorporated. The design of high flux density and low harmonic content magnetic field is also demonstrated.

This paper, studies the Power Generation Unit (PGU) subsystems of the CubeSat. Through simulation, we show the significance of solar panels and battery characteristics and power system design on the output power of the PGU. In this regard, we replace the triple junction GaAs solar panels and SAFT MP176065 batteries of an existing CubeSat called XSAT (launched by Singapore) by properties of NeXt Triple Junction (XTJ) solar cells and SAFT VES 100 lithium-ion batteries. We propose a cell layout design algorithm which increases the battery capacity and the solar array output as well as the overall efficiency. We show that through the proposed design and optimization approach, the CubeSat's ability to carry payloads during the eclipse period- in which there is no solar source to generate power- increases. In addition, we simulate and evaluate the most commonly used techniques for extracting the maximum power from satellite's solar panels under the influence of different orbital conditions. The results indicate that while in the ideal conditions, i.e. no self-spinning movements, thermal compensated fixed voltage method, with the efficiency of 86%, has the highest efficiency; it does not work well under real orbital conditions. In this paper, we propose a new solar layout design to optimize the reliability and power efficiency. This arrangement not only would ensure the high reliability of the solar system, but also it increases the efficiency and output power of the PGU without the need for changing the dimensions of solar panels.

The integration of solar energy in energy production has been steadily developing due to its abundant availability and sustainability. However, photovoltaic technology only converts approximately 20% of directed solar incidence into useful energy, and the rest is wasted in the form of heat. Recently, the drawback was tackled through the emergence of photovoltaic/thermal systems that capture both electrical and thermal energies. Through the utilization of a base fluid, excess heat is extracted from PV modules hence, improving electrical energy conversion and utilizing extracted heat for thermal applications. In this study, a performance assessment is conducted for an installed 2.88 kW hybrid PV/T system during the winter climate in Sharjah, UAE. The principal focus of this study is to assess the impact of front cooling of a PV module on electrical and thermal performance, through the utilization of water as a base fluid. Front cooling methodology improved PV module maximum power production by 9.76%, as average power generated by cooled PV module accounted to 199.8W as compared to 182.1W for the reference module. Furthermore, the average difference in generated power was accounted for 17.7W per module and an estimated 159.3W increase for all modules because of cooling. Electrical efficiency per module further reached up to 13.47% with top surface cooling as compared to 12.27% with no cooling. Inlet and outlet water temperature difference reached 2.3°C, this thermal energy can be stored for preheating applications.

With its tremendous environmental and economic potential, the renewable-energy sector is quickly gaining traction as a new growth area for many countries. Solar energy is an essential primary energy source, particularly in rural areas. In recent years, solar panels have become increasingly popular for converting solar energy to electrical energy. In this work, a new passive cooling system arrangement was planned and design. It is made up of a two identical heat sink made with four DC fans which is attached with the back part of the solar cell in order for improving the solar cell’s power efficiency by providing suitable cooling conditions. The system will consist of Temperate sensor, ATmega328P microcontroller (Arduino Nano), Heat sink, Fan, and a solar Panel (5.5v). The results showed that is the solar the temperature of the cell decreased in average output from 41.45T to 39.37 T with enhancements about 5 C % with using passive cooling system. The cooling causes to increase the average output current from 0.388 A and 0.428A with enhancements about 9.34 % for the gained current. The cooling causes to increase the average output voltage from 18.52v to 19.92v with enhancements about 7.03% for the gained voltage. The cooling causes to increase the average output power from 7.22W to 8.56W with enhancements about 13.34 % for the gained current. The cooling causes to increase efficiency with enhancements about 11% which is a good ratio that when using the cooling system.

Silicon photonics is an emerging technology allowing to take the advantage of high-speed light propagation to accelerate computing kernels in integrated systems. Micrometer-scale optical devices call for reconfigurable architectures to maximize resources utilization. Typical reconfigurable optical computing architectures involve micro-ring resonators for electro-optic modulation. However, such devices require voltage and thermal tuning to compensate for fabrication process variability and thermal sensitivity. This power-hungry calibration leads to significant static power overhead, thus limiting the scalability of optical architectures. In this paper, we propose to use non-volatile Phase Change Materials (PCM) elements to route optical signals only through the required resonators, hence saving calibration energy of bypassed resonators. The non-volatility of PCM elements allows maintaining the optical path. We investigate the efficiency of the PCM elements on the Reconfigurable Directed Logic (RDL) architecture. Results show that the static power is reduced by 32.8% on average and that 30% power saving is obtained from 158kHz reconfiguration frequency.

This work presented a stochastic computing (SC) split multiply-and-accumulate (MAC) unit that is operated using deterministic sequence and is able to achieve time latency and power reductions without accuracy degrading. In this improved deterministic SC design, the conventional Stochastic Number Generator (SNG) with large overhead is replaced with a lightweight decoder that effectively generates uncorrelated and segmented stochastic number (SN) without the need for random sources (PRNG). The proposed deterministic and split SC-MAC is implemented in ASIC 40nm technology for detailed hardware evaluation and its functionality is also verified in convolutional neural network (CNN) using MNIST data sets. The new SCMAC is found to be higher in power efficiency (GMACS/mW) and lower in energy consumption (pJ/MAC) as compared to the conventional SC-MAC as well as the prior arts.

We present an 850 nm VCSEL-based NRZ optical link operating at 50 Gbps. The full link uses no external equalization and has a power efficiency of 9.5 pJ/bit.

Low-power solutions are crucial for realizing the throughput gains of mmWave massive MIMO in base station to mobile links, particularly for the battery-powered handset. LNA power consumption is a significant bottleneck in scaling to large arrays at high frequencies. We propose a simplified phased array architecture for a 140 GHz receiver that uses activation switches in place of noisy phase shifters, allowing the relaxation of LNA gain requirements and, consequently, power consumption. On-off beamforming is employed, which introduces a tradeoff between aperture utilization and power efficiency. Our results show the potential for 7X power savings with approximately 40% average utilization of die area.

Development in the field of Single Board Computers (SBC) have been increasing for several years. They provide a good balance between computing performance and power consumption which is usually required for mobile platforms, like application in vehicles for Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD). However, there is an ever-increasing need of more powerful and efficient SBCs which can run power intensive Deep Neural Networks (DNNs) in real-time and can also satisfy necessary functional safety requirements such as Automotive Safety Integrity Level (ASIL). ProAI is being developed by ZF mainly to run powerful and efficient applications such as multitask DNNs and on top of that it also has the required safety certification for AD. In this work, we compare and discuss state of the art SBC on the basis of power intensive multitask DNN architecture called Multitask-CenterNet with respect to performance measures such as, FPS and power efficiency. As an automotive supercomputer, ProAI delivers an excellent combination of performance and efficiency, managing nearly twice the number of FPS per watt than a modern workstation laptop and almost four times compared to the Jetson Nano. Furthermore, it was also shown that there is still power in reserve for further and more complex tasks on the ProAI, based on the CPU and GPU utilization during the benchmark., Comment: Accepted by IEEE International Conference on Computer Vision (ICCV) 2021

The joint PAPR reduction and predistortion technique is the one solution to remove the nonlinear distortions of nonlinear high-power amplifier (HPA) and to increase the power efficiency. This paper can be used as a reference for the development of LTE network in future research. In this paper, we implement this joint technique at source and the predistortion technique at relay to improve the performance of cooperative communication networks amplify and forward (AF) relaying system from nonlinear distortion which are produced by HPA at source. And the relay selection strategy is used when the system is implemented in multy relay scheme. Iterative Clipping and Filtering (ICF) scheme and the cascade connection of Wiener-Hammerstein is used as the PAPR reduction and the predistortion-HPA model at source to build the joint technique. To improve the system’s performance at the relays are implemented the predistortion technique to compensate the nonlinear characteristics of memoryless non- PA with Rapp model. The system’s performance is expressed in bit error probability. From simulation results are shown that the ICF PAPR technique decreases BER performance if its CR value is low, while the predistortion technique in the joint scheme at source gives an improvement system’s performance about 4,35 dB or 15,82% at BER 10-5. Besides the predistortion technique at source, implementation of the predistortion technique at relay also gives improvement to the system’s performance and the implementation of predistortion technique both at source and at relay is shown give the best performance. Also, the applications of the relay selection strategy in more relay numbers give better performances.

Particle simulation in the field of nuclear fusion is a well-established technique which has spawned dozens of codes around the world through years (e.g. BIT1, VPIC, VSIM, OSIRIS, REMP, EPOCH, SMILEI, FBPIC, GENE, WARP, PEPC) with varying degrees of specialization for different physics areas and accessibility. Particle-in-cell (PIC) codes simulate numerous plasma phenomena on HPC systems. Today, flagship supercomputers feature GPUs per compute node to achieve unprecedented computing power at high power efficiency. PIC codes require new algorithm design and implementation for exploiting such accelerated platforms. In this work, we design and optimize simple PIC code called SIMPIC, to run on a general GPU compute node. First we provide a fully GPU SIMPIC code and show that the run time is 50 % reduced than in CPU. This code in future will be used as a test example for modifying the other more complex PIC codes from CPU to GPU.

Aggressive discretization by discretizing a metasurface into as few elements as required, can benefit the metasurface design with significantly enlarged unit cell size and lower requirement for surface impedance/phase coverage. Therefore, aggressive discretization allows one to design a metasurface with simple structure, which will potentially lead to high efficiency and broadband performance. In this work, we propose an aggressively discretized metasurface with three unit cells per period. It can realize anomalous refraction of an normal incidence to 45° with a power efficiency of 80% at the design frequency of 28 GHz, and the 3-dB power efficiency bandwidth is 13.3%. Compared to its finer discretized counterparts, our proposed metasurface achieves an improved performance using a significantly simplified design with the smallest feature size 26 -fold increased. The concept of aggressive discretization can find applications in metasurface designs in high frequencies.

This paper proposes a multiplexer based technique for accelerating matrix vector multiplication (MVM) in long short term memory networks. The concept of multiple constant multiplication with separate generation and selection of partial products is used in this design. The most important benefit of the proposed architecture is the reduced implementation complexity in terms of cell area and power efficiency. A truncating method is effectively utilized with a guaranteed reduction in the hardware complexity and power consumption. For inner product computations, the input coefficients are truncated instead of being shifted, which in turn make use of combinational circuits replacing the sequential designs. Also, to improve the overall clock period, a novel design for inner product computations is envisaged, which uses modified multiplexer architecture instead of the existing method. The results show a reduction in the implementation complexity of the MVM with a significant power reduction of 14%.

The millimeter-wave (mm-Wave) 5G hardware design requirements are considerably tougher to meet compared to their sub-6 GHz 5G counterparts, especially on the stringent power efficiency, linearity, bandwidth and cost. For the next generation 6G that utilizes Terahertz (THz) communication, its hardware design specs are expected to be even more challenging, putting a tremendous amount of pressure on the RF hardware design communities. In this paper, we will highlight some key challenges and opportunities on mm-Wave 5G and 6G hardware design for the upcoming 5G/6G revolutions.

Antenna in Package (AiP) relies on 3D packaging technology, which greatly shortens the feed line length, thereby reducing interconnection loss and improving system power efficiency. This paper briefly evaluated the performance of glass substrate as the 5G mm-wave packaging and then discusses the losses of 3 methods of the feed line. A TGV-based patch antenna is simulated at 28 GHz. The CPW feeding line between package and antenna is TGV. The TGV structure can reduce the interconnection loss and provide low dielectric loss. The proposed TGV-based patch antenna has the advantages of simple structure, bandwidth, and low loss, which can be applied for 5G communication.

Continuous-time Delta-Sigma (ΔΣ) ADCs have obtained a dominant position for the digitization in wireless receivers. With steadily improved theoretical understanding, architectural innovations and excellent circuit designs, they have achieved bandwidths of hundreds of MHz, while showing high resolution with highly competetive power efficiency. Moreover, due to their filtering properties, CT ΔΣ modulators are highly attractive for hostile receiver environments. In this review, the background and recent architectural and circuit innovations will be highlighted, including an exceeding number of hybrid designs, which improved both the application scenario as well as the power efficiency of this class of ADC. State-of-the-art examples will be illustrated and open research topics discussed.

This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).

Designing alarms for medical equipment may seem easy, but the standards' requirements combined with the nonlinearity of the acoustic transducers, with the difficulties of assessing the acoustic impedance of the transducer chamber, and with criteria such as power consumption and efficiency of the electric to acoustic conversion make the design challenging. We systematically analyze the related problems and discuss design solutions specifically for wearable alarms; examples are shown for an implemented alarm with usual driver. The main focus is on the power efficiency and the sound spectra of these alarms.

In this paper, we put forward an energy-efficient configurable asynchronous SNN accelerator for energy-constrained applications, which includes 256 neurons and 131K synapses with 8-bit fixed point weight. To achieve high energy efficiency and on-chip learning ability, we propose a sparse target propagation (S-TP) algorithm and design the accelerator with Click-based bundled-data asynchronous circuits. The SNN accelerator is implemented in 28nm CMOS process, and the post place and router (post-PAR) simulation results indicate that the SNN accelerator achieves on-chip learning with inference power efficiency of 3.97 pJ/SOP and 95.7% classification accuracy on NMNIST test dataset, which outperforms prior neuromorphic on-chip learning systems.

Crossbar resistive memory with 1 Selector 1 Resistor (1S1R) structure is attractive for low-cost, power efficient, and high-density storage class memory (SCM) applications. As technology scales down to the single-nm regime, the increasing resistivity of wordline/bitline becomes a limiting factor to device reliability. Due to the line resistance, reliability of memory cells in an array is spatially non-uniform. In this paper, by mitigating and leveraging this spatial non-uniformity, we propose two simple yet effective coding schemes, one that utilizes interleaving and one that utilizes multiple codes based on a proposed location dependent code allocation (LDCA) framework, to reduce the undetected bit-error rate (UBER) or to allow for lower write voltage for power efficiency in the studied crossbar resistive memories.

Power consumption and speed have been well determined with the help of arithmetic module, adder. So the need of high speed, error tolerance and power efficiency nature of few applications have been improved the development of approximate adders. To increase the effectiveness of integrated circuits, utilizing the tradeoff between accuracy and cost of hardware has a great potential. Various approximate adders have been proposed using this technique. By using systematic methodology, optimizing the architecture for approximate adders have been implemented. The adder is called optimized lower part constant-OR adder (LOCA). The adder has been proposed by redesigning its logic circuit.

In this work, we analyzed the static noise margin (SNM) of cryo-CMOS SRAM cells operated at superthreshold (Vdd = 0.75 V) and subthreshold (Vdd = 0.2 V) regions. The impact of the temperature and write-assist (WA) technique on the ultra-thin-body (UTB) SOI SRAM cell has been examined. UTB SOI MOSFET at 77K shows a steep subthreshold slope and reduced leakage, which enables the UTB SOI SRAM cell to operate at low Vdd. Our results show that at Vdd = 0.2V, compared to 300K, UTB SOI SRAM with WA at 77K shows 39.6%, 32.2%, and 11% improvements in read, hold, and write SNM, respectively. Therefore, cryo-CMOS SRAM enabling low Vdd operation and improving stability is a highly promising solution to improve both performance and power efficiency.

Photovoltaic thermal collector (PV/T), integrates PV modules with the thermal collector, thus simultaneously generating electrical power and heat energy. Previous studies and designs of liquid-based photovoltaic thermal collectors have focused on increasing external surface area to enhance efficiency, thereby reducing power generated per unit area of solar panels. The main objective of this paper was to enhance the thermal efficiency and electrical efficiency of PV/T by increasing convective heat transfer coefficient and internal surface area, through internally grooved tubes. Simulation is conducted where output water temperatures, current, and voltage are measured at different solar irradiation. The results show grooved tubes enhance heat transfer by 81 % and solar module electrical conversion efficiency is 17.6%.

This work presents Exynos 1080, mobile SOC which is productized in Samsung 5nm EUV technology. It is extremely power-efficient SOC which possesses four Cortex-A78 and four Cortex-A55. A Cortex-A78 is clocked at 2.8GHz and three Cortex-A78 cores are clocked at 2.6GHz. Four Cortex-A55 cores run at 2 GHz and handle light tasks. It also features the Mali-G78 MP10 GPU supporting Full HD+ displays with a 144Hz refresh rate or QHD+ displays with a 90Hz refresh rate. High-performance and low-power CPU and GPU in this work empower performance hungry mobile application. We demonstrate the architecture change to improve CPU and GPU performance compared to previous mobile processor, Exynos 980. CPU and GPU are implemented for optimal power efficiency by careful balancing of voltages and leakages, with considering heavy load scenarios. When a game scene is getting heavier, the utilization of CPU, GPU and memory controller increases and each DVFS driver changes their frequency with own policy to handle the work. Each can try to increase performance without considering other’s behavior. It leads total power increase. To solve this problem, we create AMIGO (Advanced Multi-IP Governor). It collects CPU, GPU, and memory controller data and analyzes collected data. It then decides which IP shall be boosted or suppressed to achieve target FPS or optimizes power usages of CPU, GPU, and memory controller. Amigo achieves the game power reduction by 15% on average. With high-performance CPU and GPU, Exynos 1080’s Antutu score is 89% higher than Exynos 980. The smart phones with Exynos 1080 were successfully launched in DEC 2020.

Coarse-Grained Reconfigurable Architecture (CGRA) is a promising hardware with high power efficiency, high performance and flexibility. Compiling loops with branch is a challenge to static-scheduling CGRA. Conventional mapping algorithms usually only consider coarse-grained operator placement and coarse-grained data routing. How to route fine-grained data in case of dealing with branches and other control flows is not considered. Existing CGRA architectures also have no components dedicated to fine-grained computing, storage, and routing. This paper proposes 1) a novel hybrid compiler framework including performance evaluation, the generation and optimization of data flow graphs (DFG), mapping optimization and configuration generation, which addresses control flow compilation, 2) a lightweight modification to CGRA architecture to support explicit control-flow routing and Boolean operations. Experimental results show that 1) the hybrid compiler framework can effectively extract features of branches and choose appropriate methods, 2) graph optimization and graph balance effectively reduce the size of the DFG, thereby reducing compilation time and power consumption.

Direct RF sampling receivers demand an ADC which digitized several GHz signals with the highest possible spectral purity and power efficiency. Successive approximation register (SAR) is the most popular analog to digital converter (ADC) architecture for low-speed and medium resolution. Mostly digital implementation of the SAR ADC achieves the most power efficiency and consumes the least silicon area. Due to the binary search algorithm, SAR ADC suffers from speed limitations. Charge re-distribution architecture requires a large capacitor ratio which limits the resolution. This paper presents the design considerations and possible architectures for implementations of high-speed, high-resolution, and low power SAR ADC for direct RF sampling applications and proposes a 12-bit 6-GS/s pipelined SAR hybrid ADC intended for Direct RF Sampling Receivers.

Since mobile traffic is increasing explosively, effective utilization of millimeter waves that can increase capacity is expected, but low power efficiency and blocking problem are issues. The authors are proposing a wireless communication quality prediction technology that uses millimeterwave radar for avoiding blocking problem and a network that combines a 60GHz WLAN with a mobile network in order to realize a network that is highly power efficient and can be operated stably.

Real-time edge AI systems operating in dynamic environments must learn quickly from streaming input samples without needing to undergo offline model training. We propose an FPGA accelerator for continual learning based on streaming linear discriminant analysis (SLDA), which is capable of class-incremental object classification. The proposed SLDA accelerator employs application-specific parallelism, efficient data reuse, resource sharing, and approximate computing to achieve high performance and power efficiency. Additionally, we introduce a new variant of SLDA and discuss the accuracy-efficiency trade-offs. The proposed SLDA accelerator is combined with a Convolutional Neural Network (CNN). which is implemented on Xilinx DPU to achieve full continual learning capability at nearly the same latency as inference. Experiments based on popular datasets for continual learning, CoRE50 and CUB200, demonstrate that the proposed SLDA accelerator outperforms the embedded CPU and GPU counterparts, in terms of speed and energy efficiency.

This paper presents Eciton, a very low-power LSTM neural network accelerator for low-power edge sensor nodes, demonstrating real-time processing on predictive maintenance applications with a power consumption of 17 mW under load. Eciton reduces memory and chip resource requirements via 8-bit quantization and hard sigmoid activation, allowing the accelerator as well as the LSTM model parameters to fit in a lowcost, low-power Lattice iCE40 UP5K FPGA. Eciton demonstrates real-time processing at a very low power consumption with minimal loss of accuracy on two predictive maintenance scenarios with differing characteristics, while achieving competitive power efficiency against the state-of-the-art of similar scale. We also show that the addition of this accelerator actually reduces the power budget of the sensor node by reducing power-hungry wireless transmission.The resulting power budget of the sensor node is small enough to be powered by a power harvester, potentially allowing it to run indefinitely without a battery or periodic maintenance.

The growth of the microelectronics industry has increased the demand for portable devices with three key factors such as speed, area utilized and low power consumption. For devices with high performance applications, power reduction is a major concern. The Coarse Grained Reconfigurable Architectures (CGRAs) are used in embedded systems and Internet of Things with simultaneous high programmability and high power efficiency. The CGRA’s compiler has to efficiently map the looping operations to its limited resources. One of the major problems faced is efficient mapping of applications to CGRA. Existing methods deal with the static mapping algorithms. In our proposed method we use Dynamic quick sort mapping algorithm which allows power optimization along with dynamic mapping technique. All the modules needed for the system are developed and integrated on a single chip thereby it reduce the area utilized. Thus it is called as System On Chip (SOC). Due to more flexibility in the systems, runtimes become lengthier and delay is increased. In our system the delay is reduced to 7 to 8 nanoseconds, thus effective use of CGRA is obtained along with the low power consumption and area reduction.

This paper investigates the impact of shimming strategies and scan regions on the radiofrequency (RF) induced heating near a bone screw in the ASTM phantom under 3T magnetic resonance imaging (MRI). Three shimming strategies, i.e. B1 homogeneity, focusing performance, and power efficiency, and two scan regions, head and chest, were studied. The peak RF-induced heating in terms of local specific absorption rate (SAR) is compared among quadrature source excitation and the three shimmed source excitations obtained by using a particle swarm optimization method. For the scan region of the head, all three shimming strategies can reduce the RF-induced heating. For the scan region of the chest, the shimming strategies of B1 homogeneity and focusing performance can reduce the peak SAR while the shimming strategy of power efficiency increases the peak SAR.

The currently widely used backpropagation (BP) training algorithm requires that all trainable weights in a deep neural network (DNN) be stored in memory and used sequentially in the backward path, which makes training parallelization extremely challenging and also incurs significant memory and computing overheads. Although emerging ReRAM-based computing has demonstrated great potential for DNN acceleration, state-of-the-art designs suffer from >60% energy overhead for analog-to-digital converters (ADCs). In this work, we propose PUFFIN, an efficient DNN training accelerator for Direct Feedback Alignment (DFA). PUFFIN leverages DFA to overcome the limitation of long-range data dependency required by BP and executes an L -layer DNN training in parallel in an (L+2)-stage pipeline. We implement PUFFIN using Ferroelectric Field-Effect Transistors (FeFET) due to their high performance and low-power operation. To further improve the power efficiency, we propose a random number generator (RNG) based on the statistical switching in FeFET device and an ultra-low power FeFET-based ADC. Compared to previous ReRAM-based training accelerators, PUFFIN achieves 1.3 × speedup and 2.5× improvement on power efficiency.

In last few years, research in visible light communications (VLC) based on the idea of using leds for both illumination and data communications in optical communication systems has been increasing. In this study, we propose M-ary CSK-Flip-OFDM system for optical wireless communication systems. The performance of the proposed scheme is compared with both the Flip-OFDM and classical OFDM systems in terms of bit error rate (BER) performance criteria. From the simulation results, it has been revealed that the results obtained with the proposed method provide better power efficiency than CSK-OFDM and QAM-Flip-OFDM performances.

Photovoltaic (PV) is a device that converts sunlight into electrical energy. PV will produce electrical energy according to the amount of light intensity it receives from the sun’s rays. However, in general, PV applications are installed statically, only facing one direction. It means that the PV module cannot get the maximum light intensity throughout the day. One of the efforts that can be done so that the PV module gets the maximum sunlight intensity throughout the day is to place the PV module in a perpendicular position following the movement of the sun. This is behind the creation of real-time monitoring and power point tracking tools for solar cells. This tool uses a photoresistor (LDR) sensor as a sensor and a servo motor as the PV module position’s driving force. Sunlight hitting the LDR sensor changes its resistance so that it affects the voltage value that will be received by the microcontroller analog pin. The microcontroller processes the information received from the LDR sensor and gives commands to drive the servo motor which will drive the PV module, with two axes to follow the daily pseudo motion and annual pseudo motion of the sun. This real-time monitoring and power point tracking PV tool has been tested. This tool has been able to follow the movement of the sun from East to West, obtained power of 0.001 watts for the use of LED light loads and obtained a percentage of error on the voltage sensor of 4.19% and the current sensor of 1.19%. The results of making real time monitoring show that the performance is quite efficient than the method without tracking, with a power efficiency value of 0.00649 W and this tool can monitor real time data or retrieve data once every 1 hour and 3 hours.

Mobile data traffic volume is growing on a large-scale which creates a data traffic overload problem on current cellular networks. To facilitate these growing demands for mobile data traffic volume in next-generation cellular networks such as 5G, the concept of device-to-device (D2D) communication has been introduced. D2D communications have been shown to improve power efficiency, spectrum efficiency, throughput and delay by maximizing the system’s capability in cellular networks through enabling multiple devices to communicate with each other directly. Despite these benefits, D2D communication faces some open research challenges ahead, for instance, security, cooperative multi-hop D2D communications, transmission scheduling and power control and power efficiency. This paper presents a review on the possible threats and the existing security solutions in D2D communications.