297 results on '"Endo, K"'
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2. Toward Long-Coherence-Time Si Spin Qubit: The Origin of Low-Frequency Noise in Cryo-CMOS
3. Position Control and Gas Source CVD Growth Technologies of 2D MX2 Materials for Real LSI Applications
4. Impact of La2O3/InGaAs MOS interface on InGaAs MOSFET performance and its application to InGaAs negative capacitance FET
5. Low temperature microwave annealed FinFETs with less Vth variability
6. Understanding of BTI for tunnel FETs
7. Novel wafer-scale uniform layer-by-layer etching technology for line edge roughness reduction and surface flattening of 3D Ge channels
8. PBTI for N-type tunnel FinFETs
9. Experimental study of variability in polycrystalline and crystalline silicon channel FinFET CMOS inverters
10. Accurate prediction of PBTI lifetime for N-type fin-channel tunnel FETs
11. First principles study of SiC/SiO2 interfaces towards future power devices
12. Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform
13. Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance
14. Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration
15. Hyperspectroscopic imager for baby fibers
16. Fabrication and characterization of 3D fin-channel MANOS type flash memory
17. Time resolved emission observation from top surface in avalanche breakdown of power MOSFET
18. Lowest variability SOI FinFETs having multiple Vt by back-biasing
19. Fluctuation in drain induced barrier lowering (DIBL) for FinFETs caused by granular work function variation of metal gates
20. Heated ion implantation technology for highly reliable metal-gate/high-k CMOS SOI FinFETs
21. Analysis of Vth flexibility in ultrathin-BOX SOI FinFETs
22. Charge trapping type FinFET flash memory with Al2O3 blocking layer
23. Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations
24. Analysis of threshold voltage shifts in double gate tunnel FinFETs: Effects of improved electrostatics by gate dielectrics and back gate effects
25. Suppressed variability of current-onset voltage of FinFETs by improvement of work function uniformity of metal gates
26. Experimental study of tri-gate SOI-FinFET flash memory
27. Cryogenic operation of double-gate FinFET and demonstration of analog circuit at 4.2K
28. Flexible Vth FinFETs with 9-nm-thick extremely-thin BOX
29. Comparative study of tri-gate- and double-gate-type poly-Si fin-channel split-gate flash memories
30. Comparative study of tri-gate flash memories with split and stack gates
31. Influence of fin height on poly-Si/PVD-TiN stacked gate FinFET performance
32. Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application
33. Advanced FinFET process technology for 20 nm node and beyond
34. Influence of NiSi on parasitic resistance fluctuation of FinFETs
35. Optimization of RTA process for PVD-TiN gate FinFETs
36. High-frequency characterization of intrinsic FinFET channel
37. Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET
38. Fin-height controlled PVD-TiN gate finFET SRAM for enhancing noise margin
39. 0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits
40. On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs
41. Low resistive ALD TiN metal gate using TDMAT precursor for high performance MOSFET
42. Nanoscale TiN wet etching and its application for FinFET fabrication
43. Variation analysis of TiN FinFETs
44. A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique
45. Impact of FinFET technology on 6T-SRAM performance
46. Whole body emotion expressions for KOBIAN humanoid robot — preliminary experiments with different Emotional patterns —
47. An artificial gastrocnemius for a transtibial prosthesis
48. A model of muscle-tendon function in human walking
49. Characterization of metal-gate FinFET variability based on measurements and compact model analyses
50. Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs
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