167 results on '"Endoh, T."'
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2. Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability
3. Influence of Iridium Sputtering Conditions on the Magnetic Properties of Co/Pt-Based Iridium-Synthetic Antiferromagnetic Coupling Reference Layer.
4. Effect of Magnetic Coupling Between Two CoFeB Layers on Thermal Stability in Perpendicular Magnetic Tunnel Junctions With MgO/CoFeB/Insertion Layer/CoFeB/MgO Free Layer.
5. Perpendicular Magnetic Tunnel Junctions With Four Anti-Ferromagnetically Coupled Co/Pt Pinning Layers.
6. Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage
7. Scalability of Quad Interface p-MTJ for 1× nm STT-MRAM with 10 ns Low Power Write Operation, 10 Years Retention and Endurance > 1011
8. First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology
9. A novel memory test system with an electromagnet for STT-MRAM testing
10. First Demonstration of 25-nm Quad Interface p-MTJ Device With Low Resistance-Area Product MgO and Ten Years Retention for High Reliable STT-MRAM.
11. Novel Quad interface MTJ technology and its first demonstration with high thermal stability and switching efficiency for STT-MRAM beyond 2Xnm
12. 14ns write speed 128Mb density Embedded STT-MRAM with endurance>1010 and 10yrs retention@85°C using novel low damage MTJ integration process
13. Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system
14. Structural Analysis of CoFeB/MgO-Based Perpendicular MTJs With Junction Size of 20 nm by STEM Tomography.
15. Influence of Hard Mask Materials on the Magnetic Properties of Perpendicular MTJs With Double CoFeB/MgO Interface.
16. Novel Quad-Interface MTJ Technology and its First Demonstration With High Thermal Stability Factor and Switching Efficiency for STT-MRAM Beyond 2X nm.
17. Etch Process Technology for High Density STT-MRAM.
18. High thermal tolerance synthetic ferrimagnetic reference layer with modified buffer layer by ion irradiation for perpendicular anisotropy magnetic tunnel junctions.
19. Impact of sputtering condition for tungsten on magnetic and transport properties of magnetic tunneling junction with CoFeB/W/CoFeB free layer
20. Insertion Layer Thickness Dependence of Magnetic and Electrical Properties for Double-CoFeB/MgO-Interface Magnetic Tunnel Junctions.
21. Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design
22. Impact of Tungsten Sputtering Condition on Magnetic and Transport Properties of Double-MgO Magnetic Tunneling Junction With CoFeB/W/CoFeB Free Layer.
23. Effect of series resistance on dielectric breakdown phenomenon of silicon carbide MOS capacitor
24. 10 nm\phi perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction with over 400°C high thermal tolerance by boron diffusion control
25. Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure
26. Novel oxygen showering process (OSP) for extreme damage suppression of sub-20nm high density p-MTJ array without IBE treatment
27. Diffusion behaviors observed on the surface of CoFeB film after the natural oxidation and the annealing
28. Perpendicular-anisotropy CoFeB-MgO based magnetic tunnel junctions scaling down to 1X nm
29. A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop
30. Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating
31. Improvement of Thermal Tolerance of CoFeB–MgO Perpendicular-Anisotropy Magnetic Tunnel Junctions by Controlling Boron Composition.
32. Driving Force in Diffusion and Redistribution of Reducing Agents During Redox Reaction on the Surface of CoFeB Film.
33. 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times
34. Spintronics primitive gate with high error correction efficiency 6(Perror)2 for logic-in memory architecture
35. Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme
36. A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching
37. A new vertical MOSFET "Vertical Logic Circuit (VLC) MOSFET" suppressing asymmetric characteristics and realizing an ultra compact and robust logic circuit
38. A high efficient, low power, and compact charge pump by vertical MOSFET's
39. MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
40. Floating Gate B4-Flash Memory Technology Utilizing Novel Programming Scheme - Highly Scalable, Efficient and Temperature Independent Programming -
41. A Novel 3-D Vertical FG NAND Flash Memory Cell Arrays Using the Separated Sidewall Control Gate (S-SCG) for Highly Reliable MLC Operation.
42. A New Compact SRAM Cell by Vertical MOSFET for Low-Power and Stable Operation.
43. Future High density Memory with Vertical structured device technology.
44. A unique and accurate extraction technique of the asymmetric bottom-pillar resistance for the vertical MOSFET.
45. The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the Extended Sidewall Control Gate (ESCG).
46. Design impacts on NAND Flash memory core circuits with vertical MOSFETs.
47. Proposal of a new electronic structure model of Ohmic contacts for the future metallic source and drain.
48. A compact and low power logic design for multi-pillar vertical MOSFETs.
49. Recent advance in single-ion implantation method for single-dopant devices.
50. TMR-logic-based LUT for quickly wake-up FPGA.
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