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In GaN e-HEMTs, Threshold Voltage (VTH) shift from gate voltage (VGS) stress depends on the VGs magnitude, stress time, recovery time (time between stress removal and VTH measurement), temperature and pulse polarity (0 to +VGS or −VGS to +VGS ). In this paper, unipolar (0 to VGS) and bipolar (−VGS to +VGS) pulsed gate stresses have been performed on GaN e-HEMTs with different VGS magnitudes. The pulse frequency ranges from 25 Hz to 200 kHz. The results show negative VTH shifts for unipolar VGS pulses (between 5V and 8V) at long recovery times (above 500 seconds). The VTH shift is proportional to the VGS pulse magnitude. When the recovery time is increased from 50 milliseconds to 500 seconds, the measured VTH shift becomes more negative, indicating a faster release of trapped electrons than holes. In bipolar stresses, results show both positive and negative VTH shifts with no clear magnitude or frequency dependencies.

This paper investigates the peculiarities and challenges of accurate threshold voltage ( VTH ) measurement after gate bias stress in SiC MOSFETs and GaN e-HEMTs. Traditional techniques historically used in silicon MOSFETs involve test sequences typically comprising preconditioning, VTH measurement, gate voltage stress and VTH measurement after stress. However, with Wide bandgap (WBG) devices like SiC and GaN transistors, the repeatability of VTH measurement, the impact of VTH measurement duration, delay between successive measurements and the role of preconditioning on the accuracy of VTH are currently under study. With current industrial and academic research interest in bias temperature instability in WBG devices, this paper provides significant insight into how repeatable VTH measurement is in WBG devices since measuring VTH can change it. The impact of repeated measurements on the cumulative VTH shift is investigated in both WBG technologies with different delay times between successive measurements with and without preconditioning. Unipolar and Bipolar preconditioning pulses are compared regarding VTH measurement in SiC MOSFETs.

Using experimental measurements and finite element simulations, this paper investigates the failure mode of SiC Cascode JFETs under short circuit (SC) conditions. Unlike SiC MOSFETs, where failure results in a shorted gate-source terminal (resulting from gate oxide failure), in SiC Cascode JFETs, failure usually occurs in drain-source short with the gate of the Low Voltage (LV) silicon MOSFET still operational. Measurements show that after the LV Si MOSFET gate is turned OFF, a high tail current results in the Cascode drain terminal with the drain-source voltage falling to approximately half of the blocking voltage, suggesting that the JFET is in linear mode. Finite element simulations show that thermally generated carriers in the JFET depletion region cause high leakage currents through the internal JFET gate terminal capable of turning-ON the JFET (after turn-OFF of the LV Si MOSFET) into linear mode. The measured short circuit withstand time (SCWT) is shown to be independent of temperature unlike silicon MOSFETs where the SC withstand time increases with the initial temperature.\ud

A new packaging structure for clamping the temperature of a thyristor die is analysed in this paper. The proposed structure aims to absorb the heat released from the thyristor during a short circuit protection operation, to maintain the temperature within a defined range even when the current through the thyristor is temporarily very high. The defined range is below the maximum tolerable temperature and is controlled by using phase-change material (PCM). This has the potential to reduce both space and cost when compared to traditional packaging structures which utilise heat sinks. In the course of this investigation, a thermal model of a thyristor is used for comparison. COMSOL Multiphysics was used to simulate the thyristor temperature during a fault and the effect that the PCM has on the thyristor temperature. Experiments have been performed to verify the models and validate the feasibility of the proposed concept.