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The advent of graphene and related 2-D materials has attracted the interest of the electron device research community in the past 14 years. The possibility to boost the transistor performance and the prospects to build novel device concepts with 2-D materials and their heterostructures has awakened a strong experimental interest that requires continuous support from modeling. In this paper, we review the state of the art in the simulation of electron devices based on 2-D materials. We outline the main methods to model the electronic bandstructure and to study electron transport, classifying them in terms of accuracy and computational cost. We briefly discuss, how they can be combined in a multiscale approach to provide a quantitative understanding of the mechanisms determining the operation of electron devices, and we examine the application of these methods to different families of 2-D materials. Finally, we shortly analyze the main open challenges of modeling 2-D-based electron devices. [ABSTRACT FROM AUTHOR]

We present a simulation study of silicon nanowire transistors, based on an in-house code providing the self-consistent solution of Poisson, Schrodinger, and continuity equations on a generic three-dimensional domain. The main assumption, based on the very small nanowire cross section considered, is that an adiabatic approximation can be applied to the Schrodinger equation, so that transport occurs along one-dimensional sub- bands. Different subband transport models are considered, such as ballistic transport, either including quantum tunneling or not, and drift-diffusion. We show that nanowire transistors exhibit good control of short channel effects, and that barrier tunneling is significant in the strong inversion regime even for longer devices, while it is significant in subthreshold only for the shortest channel lengths. Finally, we show that a subband-based transport model allows to reach a very good trade off between physical accuracy of the simulation and computing time. [ABSTRACT FROM PUBLISHER]

A coupled mode space approach within the nonequilibrium Green's function formalism is presented, which allows performing simulations of realistic carbon nanotube field-effect transistors (CNT-FETs) with no spatial symmetry. Computing time is significantly reduced with respect to the real space approach, since only few modes are needed in order to obtain accurate results. The advantage of the method increases with increasing nanotube diameter, and is a factor of 20 in computing time for a (25,0) nanotube. As a consequence, computationally demanding simulations like those required by a statistical investigation, or by a device performance study based on the exploration of the design space, become more affordable. As a further test of the method, we have applied the coupled mode space approach to double-gate CNT-FETs devices and devices with discrete distribution of doping atoms. In the latter case, nonballistic transport due to elastic scattering with ionized impurities in doped source and drain extensions occurs. We show that even in the case of very rough potential, the coupled mode space approach is accurate with very few modes, enabling atomistic simulations of statistical properties with reduced computational resources. [ABSTRACT FROM PUBLISHER]

In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schrödinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO2 dielectrics and high-κ stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance. [ABSTRACT FROM AUTHOR]

Since their discovery in the early 1990s, the interest in carbon nanotube (CNT) electronics has exploded. One main factor that controls the device performance of CNT field-effect transistors (CNT MOSFETs) is the electronic structure of the nanotube. In this paper we use three different bandstructure models: 1) extended Huumlckel theory (EHT); 2) orthogonal pz tight-binding (OTB); and 3) parabolic effective mass model (EFM) to investigate the bandstructure effects on the device characteristics of a CNT MOSFET using semiclassical and quantum treatments of transport. We find that, after proper calibration, the OTB model is essentially identical to the EHT over the energy range of interest. We also find that an even simpler parabolic EFM facilitates CNT MOSFET simulations within practically applied bias ranges [ABSTRACT FROM PUBLISHER]

We present an approach, and its implementation in a computer program, for the three-dimensional (3-D) simulation of realistic single electron transistor (SET) structures, in which subregions with different degrees of quantum confinement are simultaneously considered. The proposed approach is based on the self-consistent solution of the many body Schrodinger equation with density functional theory and on the computation of the conductance of tunnel constrictions through the solution of the 3-D Schrodinger equation with open boundary conditions. We have developed an efficient code (ViDES) based on such an approach. As examples of addressable SET structures, we present the simulation of a SET, one defined by metal gates on an AlGaAs/GaAs heterostructures, and of a SET defined by etching and oxidation on the silicon-on-insulator material system. Since SETs represent prototypical nanoscale devices, the code may be a valuable tool for the investigation and optimization of a broad range of nanoelectronic solid-state devices. [ABSTRACT FROM PUBLISHER]

In this paper, we present an approach based on three-dimensional simulations for the investigation of the dependence of the programming window of silicon-on-insulator (SOI) nanocrystal memories on the width of the silicon channel. Recent experiments show that the threshold voltage shift after programming increases with decreasing channel width. By evaluating the consequences of possible assumptions on the charge stored in the nanocrystals, we show that such behavior can be consistently explained by the preferential injection of electrons, during the program operation, through the oxide near the edges of the channel. As a consequence, charge is mostly stored in the dots close to the edges and, therefore, is more and more effective as the channel width is decreased. Experiments and simulations on SOI nanocrystal memories show support of our interpretation with respect to different proposed mechanisms. [ABSTRACT FROM PUBLISHER]