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This paper presents a CMOS image sensor and an AI accelerator to realize surveillance camera systems based on edge computing. For CMOS image sensors to be used for surveillance, it is desirable that they are highly sensitive even in low illuminance. We propose a new timing shift ADC used in CMOS image sensors for improving high sensitivity performance. Our proposed ADC improves non-linearity characteristics under low illuminance by 63%. Achieving power-efficient edge computing is a challenge for the systems to be used widely in the surveillance camera market. We demonstrate that our proposed AI accelerator performs inference processing for object recognition with 1 TOPS/W. Keywords: CMOS image sensor, surveillance camera system, low light imaging, AI accelerator, edge computing

This paper proposes a novel circuit and technique for high accuracy measurement of analog-to-digital converters (ADCs) within a CMOS image sensor (CIS) chip. The evaluation of such ADCs has been a big challenge because optical signal source for CIS input is difficult to manage and control. The test circuit provides a dual path, one for normal operation and the other for applying external electrical input signal directly to ADC. This test path also has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics. This test circuit and technique enables the measurement of ADC characteristics directly from CIS chip. Measured result shows INL of 15 LSB, crosstalk of 20 LSB and accelerated column interference of 5 LSB. These measured results agreed with the designed values. With this straightforward circuit and technique, we confirmed the measurement accuracy of 14-bit.

A 5.0G-pixel/s readout circuit for 15.3mm×8.6mm optical size, 3.7M-pixel, 1300 fps, and digital output image sensor is presented. To achieve 5.0G-pixel/s readout rate, the high speed column readout circuit is introduced. The novel pixel readout, A/D conversion, and digital data transfer schemes are introduced to realize the readout rate and to reduce the interference noise. The 1 horizontal (1H) readout time is realized to be 1.0μs.

For low power consumption which makes more than doubles a battery life, the charge-recycling system by reuse the energy between the two or more CPUs and the task scheduling technique for high efficiency are proposed. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. To control divided loads, a high speed and efficient regulator are needed. The internal circuit voltage variation between upper and lower modules is solved by seven LDO regulators, boosting switched capacitor and the tank capacitor. As a result, the stable voltage can be supplied to each CPU, even if upper and lower loads are different or battery is used. The LDOs improve the margin of accumulation of tank capacitor or task schedule operation, and the power efficiency is raised further. The system can be on-chip without external large control circuit and inductor like switching regulator. The test chips were fabricated using 90nm standard CMOS technology. Although the power efficiency of the conventional system with a simple LDO is 44.4% at the maximum, that of the proposed charge-recycling system improves to 88.9%.

Low DropOut Converter (LDO) is commonly employed as voltage down converter (VDC) because of its high compatibility with System on Chips (SoCs), but in general, LDO is not so high power efficient. This paper presents an Autonomous Controlled Cascaded LDOs power system which achieves about doubled power efficiency of the conventional LDO systems. In proposed architecture, existing logic circuitries are divided into two load group, and electrical charges are shared among the blocks and a tank circuit. We confirmed that our architecture makes effective use of 88.9% of the battery energy by simulation which is comparable to that of switching regulators whereas ours is easier to implement in SoCs.1

SOI device is promised to be a mobile and wireless network applications as it has better potential of high speed, low operating voltage and Q-factor. Gate Body directly connected SOI MOSFET suppresses Sees historical effects and is promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

TTRAM can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. The enhanced TTRAM (ET2RAM) can solve these issues and the key technologies provide 0.5V memory operation, compact and higher sensitivity sense amplifier, and programmable multi-bank array

SOI device has the better potential of high speed, low operating voltage and RF functions like as mobile and wireless network applications. Gate Body directly connected SOI MOSFET without historical effects is one of the promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

We had reported TTRAM (Morishita, 2005) and ET2RAM (Arimoto, 2006) which are high-density capacitor-less SOI-CMOS compatible memory IP's. A platform design methodology becomes the main stream in SoC world because the system integration progress and complexity requires the implementation of many lands of IP's and induces the longer design turn around time and design cost up. This time, we have up-graded ET2RAM with scalable function named SETRAM (scalable enhanced twin-transistor RAM). This memory IP can be applied to the many kinds of applications by the verify control technique with compact ABC (automatic body control) sense amplifier. The scalable functions are, for example, 263MHz high speed random cycle memory to replace the high density on chip SRAM, 79mW/4Mb lower active power dissipation for mobile application, 453MHz data transfer of page/burst mode for cache memory and graphics memory applications and lower stand-by current mode of 5 sec data retention time. These are also supported as the programmable functions. The SETRAM can provide the scalable memory IP's in SoC platform on SOI devices and can improve the performance of many future applications

This paper describes a novel TCAM architecture with associated embedded DRAM. The design concept improves the soft error immunity by 6 digits, and also resolves the critical problems of the look-up table maintenance of TCAM. The proposed architecture in this paper is especially attractive for realizing soft-error immune, high-performance TCAM chips.

In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltage SoC design that consist of the adaptive voltage management (AVM). The proposed AVM accurately controls to set the most suitable voltage level with table look-up method. This PVT control system realizes wide operating margin, DFM function for low voltage SoC. The experimental chip is fabricated on 90nm CMOS process and confirmed the proposed architecture accurately controls the voltage level and the operation margin securing at the lower voltage

An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13/spl mu/m low-power process and it achieves 312MHz random cycle operation. Data retention power is 73/spl mu/W, which is 5% compared to a conventional one.

A novel body potential controlling technique for floating SOI CMOS circuits is proposed and verified. High speed operation is realized with a small chip size by using body-floating SOI transistors. By using this technique, the threshold voltage of the body-floating transistors is varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced less than 1/10th compared to the non-control operation of the body potential and operates at high speed during the active period. There is no access penalty for the recovery operation from the standby mode. This technique supports sub 1 V operation, which is required for future battery operated devices with wide range covering.

Embedded DRAM (eDRAM) macros have been proposed as away to achieve the low power and wide bandwidth required by graphic controllers, network systems, and mobile systems. Currently, these applications require a reduction of design turn-around time (TAT) for the various specifications, as well as lower-voltage operation. Conventional eDRAM is generated by placement of hardware macros that are designed beforehand. The hardware macro restricts eDRAM specifications, and many hardware macros are necessary to support the demands of different customers. An eDRAM architecture that provides only the interface component as a software macro, i.e., hardware description language (HDL), has been recently reported. However, in this architecture, adjusting of control signal delays and differing control circuits are necessary for each memory configuration. The architecture reported here provides reduction of design TAT, more than 120 k eDRAM configurations, 1.2 V (100 MHz) to 1.8 V (200 MHz) operation, and a flexible interface. In addition, an enhanced on-chip tester tests the various eDRAM macros, reducing test time to 1/64 with a simultaneous 512 b I/O pass/failjudgment, and performs repair analysis at speed testing conditions.

Advanced 3D graphics (3DG) technology will be used in console game machines, and it is desired to develop a rendering controller chip which can handle real time 3D animation with true colors. Embedded DRAM (eDRAM) technology attracts attention of the 3DG systems, because only eDRAM can satisfy the required data rate. Four or more pipelines, 200 MHz pipeline operating frequency, and 64 b per pixel are required. With this configuration, the required data rate is 39.4 GB/s, assuming the total penalty of 35% for page miss and video refresh. Furthermore, a 120 Mb frame buffer is required for a 1280/spl times/1024-pixels screen. This 0.18 /spl mu/m 32 Mb eDRAM macro satisfies these requirements.