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Diabetes Mellitus (DM) is the group of diseases where the patient suffers from higher levels of sugar in blood over a prolonged time. Machine learning classifier helps to predict the disease based on the condition of the symptom suffered by the patient. The aim of this paper is to compare the performance of the machine learning tree classifiers in predicting Diabetes Mellitus (DM). Machine learning tree classifiers such as Random Forest, C4.5, Random Tree, REPTree, and Logistic Model Tree (LMT) were analyzed based on their accuracy and True Positive Rate (TPR). In this analysis of predicting diabetes mellitus Logistic Model Tree (LMT) machine learning tree classifier achieved higher accuracy of 79.31%, True Positive Rate (TPR) of 0.739 and an execution time of 1.09 sec than other classifiers under study.

This paper describes a top-down approach to design a Sigma-Delta based modulator for analog to digital conversion. The primary focus is on designing an ADC for audio application, thus, the conversion is done on a 22.05 kHz bandwidth with a 16-bit resolution (CD quality). The behavioural code of the modulator is created first to check the signal ranges on internal nodes. Next, the circuit non-idealities, such as, finite Op-Amp gain, finite latency of Op-Amp and comparator offset are introduced to derive the tolerable limits and the specification of sub-blocks. Later, the individual blocks are carefully designed in 0.35 μm CMOS technology and are integrated. SPICE-based simulation is carried out on the entire circuit and the results are validated with MATLAB.

This paper describes a 8-bit 22.5 MS/s Asynchronous Analog to Digital Converter (A-ADC) employing a Successive Approximation Register (SAR) architecture. The proposed system relies on single rail encoded handshaking signals to transfer data between functional blocks and perpetuates its conversion cyclically without an external clock. The components of the design are self-timed by employing completion detection techniques and takes about the same silicon area as an equivalent synchronous implementation. Due to the asynchronous operation the system's sampling rate goes up twofold, as the timing constraints are dynamically generated. The FoM of the ADC is 1.77 pj/conversion-step.

In essence, the goal of data mining is to extract knowledge from data. Data mining is an inter-disciplinary field, whose core is at the intersection of machine learning, statistics and databases. J2ME services play an important role in the field of Communication industry. In this paper, we discuss and analyze the consumptive behaviour and a detailed analysis of Ant Colony Algorithm for implementation of object pool optimization. We also discuss some of the wireless technologies like CLDC, MIDP and RMS so that our comprehensive study can achieve the goal of implementation of Object Pool. The goal is to discover knowledge that is not only accurate but also comprehensible based on Ant Colony algorithm.