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The existing super-resolution methods have the problems of blurring contour and losing details, which cannot make full use of the internal and external information of the image. On the basis of convolutional neural network, a super-resolution model embedded in Transformer module is proposed. Through the fusion of CNN and Transformer, image feature extraction and corrupted information recovery are performed. The training process is divided into an unsupervised pre-training process on the ImageNet subset and a supervised fine-tuning training process on the DIV2K data set. Contrastive loss is introduced into the loss function to achieve the consistency of super-resolution image category and texture. It is compared with the current mainstream image super-resolution methods on the standard 5 benchmark data sets. Experiments show that compared with other algorithms, this algorithm can better recover the high-frequency information of the image, and generate super-resolution results with clear details and fine structure.

Practical Byzantine Fault Tolerance (PBFT) algorithm is a popular solution for establishing consensus in blockchain systems. However, there are some issues in the PBFT algorithm, such as high energy consumption, low efficiency, and poor scalability. These problems are not solved even in some of its improved algorithms, such as Byzantine consensus algorithm based on Gossip protocol (GBC) and Credit Practical Byzantine Fault Tolerance (CBPFT) algorithms. To address these issues, this paper proposes a Byzantine Fault Tolerant algorithm based on Vote algorithm (vBFT). The nodes in the network are divided into three types of with different responsibilities by the vBFT algorithm, which are client, slave, and master nodes. The state between nodes could be dynamically adjusted at any time. As shown our simulations and analysis, the proposed algorithm has significantly improved performance in terms of dynamics, energy consumption, fault tolerance and low-latency compared with consensus algorithms such as PBFT, GBC and CBPFT algorithm.

Image description is a comprehensive task combining natural language processing and computer vision. This paper proposes a model improved by GRU for the lack of long-term memory due to use of ordinary RNN in m-RNN. The new model can predict the words at the next moment based on the information at the previous moment, and generates a complete image description sentence. Moreover, using the MSCOCO2014 dataset, our model was trained and tested, and the indicators such as BLEU, METEOR and CIDEr are used as evaluation criteria. The experimental comparison with the original model and other models is carried out to further verify the validity of our model.

In this paper, a linear frequency modulated continuous wave (LFMCW) radar system was designed and established for detecting the distance and velocity of people and vehicles. The radar operates at 35 GHz with the maximum sweep frequency band of 2 GHz and uses triangular wave modulation. Background learning method is introduced to improve the system performance. Learning and recording the stationary background results after Moving Target Indication (MTI) filter is used as the threshold value for detecting moving targets. The designed radar system measured the distance and velocity of walking people and the speed error is less than 0.5 m/s.

In this paper, a distributed-antenna electric power communication network is considered with multiple distributed antennas as access, points serving multiple terminals. We investigate the energy efficiency (EE) of the network. In order to promote the network EE with guaranteed quality of service of terminals. We first derive the approximate EE expression of the distributed network. Accordingly, we then propose an access point selection algorithm based on the distance between terminals to stations in order to maximize the network EE while not affecting the overall networks spectral efficiency too much. Numerical results show that the network EE of the proposed algorithm outperforms the conventional method with all antennas selected. It is observed that trivially increasing the number of antennas access points always guarantee a high EE. Simulation results verify the effectiveness of the proposed method.

The design and simulation of a novel high-speed programmable counter circuit for 5GHz frequency synthesizer application in WLAN is presented. Compared with the conventional programmable counter circuit, it has a higher speed by using high-speed dual modulus prescaler (DMP) architecture that can operate as fast as asynchronous divider circuits and a new programmable counter structure. The proposed DMP circuit makes uses of the character of asynchronous circuits to increase running frequency. Based on this topology, a programmable counter is implemented in 0.18 mm TSMC standard CMOS process. Simulation result shows that a maximum operating frequency 6.3GHz is obtained at 1.8V supply voltage with a power consumption of 6.7 mW for the proposed DMP architecture and that a maximum operating frequency 4GHz is obtained at 1.8V supply voltage for the conventional DMP using the same synchronous part. Simulation result also shows that the proposed programmable counter can operate between 0.1GHz and 6.3GHz correctly.

A new architecture for integrated wideband PLL (phase locked loop) based frequency synthesizer is presented. The largest achieved tuning range is depended on the largest available power supply in a system. A method of multiple power supplies has been used to produce the large tuning range with a low VCO (voltage controlled oscillator) gain, which can reduce the level of reference spurs. A prototype, which is the integer-N PLL-based frequency synthesizer, is designed and fabricated in TSMC 0.18mm CMOS 1p6m+ process. Measurements show that the tuning range at center frequency 800MHz is more than 80MHz when the available largest power supply is 3V, and the phase noise performance is -100dBc/Hz at 1MHz offset from carrier and the frequency spurs is -110dBc/Hz with 4MHz reference frequency. The presented circuit consumes 50mW and occupies a die area of 1mm2.

Conventional CMOS frequency synthesizers have limited tuning range. The limited tuning range make the RF front-end need special technology to meet the frequency specification of wideband communications. A new architecture for an integrated wideband phase locked loop (PLL)-based frequency synthesizer is presented. The largest achieved tuning range is dependent on the largest available power supply in a system. A method of multiple power supplies has been used to produce the large tuning range with a low voltage controlled oscillator (VCO) gain which can reduce the level of reference spurs and realize 200 kHz or 1 MHz channel bandwidth. A prototype, which is the integer-N PLL-based frequency synthesizer, is designed and simulated using the TSMC 0.18 /spl mu/m CMOS RF model. The tuning range at center frequency 1.1 GHz is more than 250 MHz when the available largest power supply is 3 V.

Incorporating the low-IF architecture, a 5-GHz WLAN receiver front-end chip is implemented in a 0.18 /spl mu/m in CMOS technology. The chip contains a single-in differential-out low noise amplifier with 1.5dB noise figure (NF), 25dB voltage gain and less than 13mW power consumption, a folded structure downconversion mixer with 9.9dB single side band noise figure (SSB NF), 13.7dB voltage gain and +2.7dBm IIP3, consuming 10mA current under a 2V supply voltage. The chip also has a 12dB gain adjustment through a VGA cell placed in parallel with LNA's input.

A dynamic Direct Current (DC)-offset canceller in a receiver of a communication system is presented. The dynamic DC-offset voltage is sampled and then a loop architecture is used to cancel the DC-offset voltage. The simulated results show that the DC-offset voltage is no more than 5 mV after the loop architecture is operated.

Firstly, a prototype circuit of 5GHz fully integrated CMOS quadrature voltage controlled oscillator (QVCO) realized in TSMC 0.18mm CMOS technology. The QVCO could be tuned between 5.75 GHz and 5.95 GHz, and shows a phase noise of -105dBc/Hz at 5MHz offset frequency from the carrier by testing the one-side of the differential outputs, for a current consumption of 10mA from a 1.8V power supply. Then, some design aspects on QVCO are analyzed focusing on the optimization of phase noise. According to the optimizing methods of phase noise, QVCO is classified into two types. At last, a design guide is proposed and a new QVCO architecture is predicted that has better phase noise in QVCO in future.

This paper presents a 2.4 GHz energy-efficient phase-locked loop (PLL)-based transmitter (TX) integrated in 0.18-μm CMOS technology. By using Twin-VCO transmission scheme, the data rate of the transmitter is free of loop bandwidth of PLL with stable carrier frequency. The frequency presetting technique is adopted to not only reduce the lock-in time of the PLL but also minimize the VCO gain (KVCO) variation. Measured results show that the frequency precision of the Twin-VCO relative to center carrier is less than 21 ppm. The lock-in time of the PLL is less than 7 μs. The TX dissipates 11.6 mW when the output power is 0 dBm at a data rate of 18 Mbps and achieves an energy efficiency less than 0.64 nJ/bit.

To bridge the gap between limited energy supplies of the sensor nodes and the system lifetime, duty-cycle Wireless Sensor Networks (WSNs) with data aggregation are studied in this paper. We proposed a load-balanced and latency-efficient data aggregation scheduling for duty-cycled WSNs. A shortest path tree (SPT) is used as the routing structure for data aggregation scheduling. In SPT, parent-children assignments are well-designed to assign nodes from level h+1 to the parents at level h such that every parent has a balanced load, while reducing the sleep latency which is a period of time for a sender to wait for its parent to be active. Finally, through the simulation and comparisons, we prove the effectiveness of our approach.

This paper proposes a novel concatenated channel codec for WBANs. It has been used in baseband transceiver to achieve low power consumption, high energy efficiency and high coding gain. It consists of variable-length Reed-Solomon (VL-RS) code, Hamming code, CRC code and Proactive Reed-Solomon Bypass (PRSB) circuits. This structure improves system code gain minimum 4dB and maximum 7.8dB at Bit Error Rate (BER) 10−3. It uses PRSB technique to proactive reduces the power consumption of decoding according to channel quality. It is designed in 0.18um CMOS technology. The lowest power consumption of whole baseband transceiver is 6.1 µW for TX and 7.2 µW for RX at 1.0V. Its energy efficiency is 19.6 pJ/bit for TX and 24.5 pJ/bit for RX at 5 Mbps.

An analog baseband chain for a low-IF Zigbee receiver is implemented in a 0.18-µm CMOS process. The analog baseband consists of a variable gain complex channel filter with on-chip automatic frequency tuning and two decibel linear programmable gain amplifiers (PGA). The phased-locked loop (PLL) based master-slave frequency tuning scheme keeps the complex filter characteristic immune to process and temperature. Measurements results indicate that the analog baseband provides a gain control range from 9 dB to 65 dB. The analog baseband dissipates 2.51mA from a 1.8 V supply and the chip core area is 0.85mm2.

A low power PLL quadrature frequency synthesizer for Zigbee applications is presented. The current reusing and forward-body bias techniques are applied to decrease power consumption and to improve noise characteristic of the synthesizer. The synthesizer is implemented in 0.18μm CMOS process and the core chip area is about 1.2×1.2mm2. Measured results show that the frequency tuning range is 2.04–2.49GHz and the locking time is less than 75μs. The phase noises are −110.4dBc/Hz and −125.5dBc/Hz at the offset of 1MHz and 10MHz, respectively. The reference spur is −68.45dBc at the offset of 2.5MHz. It consumes only 3.2mA current at a 1.8V operating voltage.

This paper presents a novel low power baseband transceiver for wireless body area network (WBAN). This design includes a low complexity physical layer which is compatible with IEEE 802.15.4 and one optimal baseband operating scheme to reduce system power consumption. And the proposed channel codec has been integrated to improve anti-noise performance and energy efficiency. The chip is fabricated in 0.18 μm CMOS technology. The lowest power dissipation is 6.1 μW for TX and 7.2 μW for RX at 1.0V. Measurement results show energy efficiency is 19.6 pJ/bit for TX and 24.5 pJ/bit for RX at 5 Mbps.

The unmanned nature of wireless sensor networks make them very vulnerable to the malicious attacks. Therefore, how to complete secure data collection under different conditions is the crucial issue to wireless sensor networks. There have been a few on-going research efforts about multipath routing for secure data collection. In this paper, we make full use of the broadcast message when wireless sensor network initializes to construct secure multipath routing for secure data collection which will cause little overhead to the sensor nodes in the network. In accordance with the simulation results, the algorithm in this paper compares with other recent researches is better.

In order to make full use of multi-IO signals to control equipments, a new type of universal IO controller based on Windows CE and C# is developed. It uses ARM9 as microprocessor, Windows CE as operation system and C# as programming language, and the multi-IO interfaces are extended by means of a simplified ISA bus and a FPGA chip. Two working modes are realized, local manual control and remote command control (via TCP/IP protocol), with such advances as friendly GUI and good extending ability. The applying effect of this controller now used in a engineering equipment manifests its steady performance.

To meet the requirement of high-speed data processing of complicated system with multi-sensor inputs and multi-controller outputs, an embedded ARM+FPGA +DSP multiprocessor platform is designed, which is characterized by synchronous cooperation and mutual exchange of shared data. ARM completes interface expansion and task scheduling configuring peripheral interfaces including RS422, CAN and RJ45, and it loads program into the 3 DSPs via HPI bus. Shared data stored in multi FIFO core sets in FPGA can be transmitted between any two processors controlled synchronously by interrupt signal. The interrupt signal from ARM starts a new turn of operation, in which period all processors exchange necessary shared data mutually, after ARM collecting 3 DSP interrupt signals, it means the end of this turn and the beginning of next operation cycle. With characters of high-speed, synchronization and real-time, this system platform is designed for the semi-physical simulation system suitable for the on-orbit spacecraft ground test. The principle and frame have reference value for navigation computer upgrading improvement.

A low phase noise, large tuning range VCO is implemented using 0.25 um CMOS process. The new method, which can enlarge the tuning range and improve phase noise of CMOS VCO, is presented in this paper. It combines the dominant parallel resonance using standard passive on-chip spiral inductors and the additional series resonance using active inductors consisted of MOSFET, resistor and capacitor. Without others parameters variation, the general VCO can form the proposed VCO by adding two resistors and two capacitors; and the proposed VCO has the same power consumption as the general VCO, which is 10 mW in this design. As for the performance, the tuning range of the proposed VCO is improved 6% and the achieved highest frequency is improved about 13%. Also, it is the most important that the phase noise is improved up to 15 dB at most.

This paper presents a fully integrated CMOS IEEE 802.11b/g WLAN radio transceiver chip with a novel local oscillator (LO) leakage auto calibration scheme. The transceiver chip is based on direct-conversion transmitter and receiver architecture and integrated in 0.25mum CMOS process. The noise figure is less than 5dB in a receive path. The inherent LO-leakage of direct-conversion transmitter is cancelled perfectly by using the proposed auto calibration method. The consumption currents of the receiver and transmitter are 120mA and 110mA at 2.5V power supply, respectively. Many kinds of cards and APs, which is made of this radio chip and homemade BB+MAC chip, have come into market.

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18/spl mu/m CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

The paper presents a fully integrated two-receive-path and one-transmit-path CMOS radio transceiver chip compliant with 2.4GHz IEEE802.11b/g WLAN standards. The transceiver chip is based on direct-conversion architecture and integrates LNAs, mixers, filters, VGA, frequency synthesizer with on-chip VCO and voltage reference circuit in 0.25/spl mu/m CMOS process. It can improve the SNR characteristic of the communication system about 3/spl sim/6 dB. It increases the cover-range and reduces the influence of the multipath effect significantly. The noise figure is less than 5dB in a receive-path. The consumption currents of the receivers and transmitter are 120mA and 110mA at 2.5V power supply, respectively.