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The performance of theoretical ultrahigh-voltage power semiconductor devices has been predicted by means of numerical simulations using the Sentaurus technology computer-aided design tool. A general silicon carbide punch-through insulated-gate bipolar transistor (IGBT) structure has been implemented with suitable physics-based models and parameters to reflect the device characteristics in a wide range of device blocking voltages from 20 to 50 kV. The models for 20 kV class IGBTs have been implicitly validated by means of published experimental results. Mixed-mode simulations were performed that predicted total switching energy loss densities of 335, 629, 906, and 999 mJ/cm2 for 20, 30, 40, and 50 kV class devices, respectively, at 25 °C, JC = 20 A/cm2, and an ambipolar carrier lifetime of 20 μs. While the IGBT on-state forward voltage drop reduces, the switching losses increase with higher charge-carrier lifetime for a given current density (e.g., 20 A/cm2). The large span of simulation results will be used as an input support to the design of future high-power converters. [ABSTRACT FROM AUTHOR]

In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance (${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$) and threshold voltage (${V}_{\text {th}}$) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times (${T}_{r}$ and ${T}_{f}$) and the corresponding energy loss (${E}_{r}$ and ${E}_{f}$) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

A high gamma radiation hardness of 4H-SiC circuits is performed. The OR NOR circuits are based on emitter coupled logic (ECL), using integrated bipolar NPN transistors. Gain degradation in individual bipolar junction transistors (BJT) is minimal up to a dose of 38 Mrad (SiO2), but for the dose of 332 Mrad (SiO2) a degradation of 52% is observed. The SiC BJTs show higher radiation hardness than existing Si-technology and high stability under temperature stress. It is proposed that the oxide charge-dominated recombination is the key base current recombination mechanism contributing to gain degradation. An improvement in the gain is seen after annealing at 400 °C for 1800 s due to the possible annealing of some of the oxide defects contributing to the oxide charge. [ABSTRACT FROM PUBLISHER]

Radiation effects of 3-MeV protons on 4H-SiC bipolar devices and integrated OR-NOR gates have been investigated. The chips were irradiated from a fluence of 1 \times 10^8~\cm^-2 until 1 \times 10^13~\cm^-2. Up until a fluence of 1 \times 10^11~\cm^-2, both the bipolar devices and the logic gates were found to be stable, but for higher fluence, they begin to degrade as a function of irradiation fluence. Using TCAD simulations, degradation of the transistor current gain has been found to be more dominated by surface states than bulk defects generated by the proton irradiation. Simulations of logic circuits using SPICE show that the gain degradation is the key contribution to the unstable performance of the circuits from the fluence of 1 \times 10^12~\cm^-2 and above. [ABSTRACT FROM PUBLISHER]

The influence of bulk traps in different regions of 4H-SiC bipolar junction transistors (BJTs) is investigated. The investigation is based on experimental results obtained by implanting up to \10^11\cm^-2 fluences of helium ions in the collector region. The results indicate that implantations, creating point defect concentrations in the range of the doping level, produce a sufficiently high concentration of traps to reduce the carrier concentration in this specific region. These traps degrade the device characteristics and are irrecoverable up to 500 ^\circ\C annealing. The experimental results are qualitatively analyzed by device simulations using a 2D numerical computer-aided design tool (TCAD). Systematic simulations are then performed by introducing traps at different locations in the BJT (i.e., emitter, base, and collector regions). The results indicate that the device performance is highly dependent on the defect concentration in the base region. The defects at different levels inside the collector also influence the device by producing a compensated layer in the material. However, the same concentration of defects (i.e., \sim\10^15\ \cm^-3) has less influence in the emitter region. [ABSTRACT FROM AUTHOR]

Degradation of \SiO2 surface passivation for 4H-SiC power bipolar junction transistors (BJTs) as a result of ion irradiation has been studied to assess the radiation hardness of these devices. Fully functional BJTs with 2700 V breakdown voltage are implanted with 600 keV helium ions at fluences ranging from \1 \times \10^12 to \1 \times \10^16\ \cm^-2 at room temperature. These ions are estimated to reach the \SiO2/ \SiC interface. The current–voltage characteristics before and after irradiation show that the current gain of the devices starts degrading after a helium fluence of \1\times \10^14\ \cm^-2 and decreases up to 20% for the highest fluence of ions. Simulations show that the helium ions induce ionization inside the \SiO2, which increases the interface charge and leads to a degradation of the BJT performance. Thermal annealing of the irradiated devices at 300 ^\circ \C, 420 ^\circ\C, and 500 ^\circ\C further increases the amount of charge at the interface, resulting in increased base current in the low-voltage range. [ABSTRACT FROM AUTHOR]

The fabrication and performance of planar InAs/AlSb high-electron-mobility transistors (HEMTs) based on ion-implantation isolation technology are reported. Ar atoms have been implanted at an energy of 100 keV and with a dose of \2 \times \10^15\ \cm^-2 in order to induce device isolation. The InAs/AlSb HEMT exhibited a maximum drain current of 900 mA/mm, a peak transconductance of 1180 mS/mm, and an fT/f\max ratio of 210 GHz/180 GHz at a low drain bias of 0.3 V. The combination of excellent stability against oxidation with the high device isolation demonstrated by the implantation technique can dramatically improve the suitability of InAs/AlSb HEMTs for high-frequency and ultralow-power MMIC applications. [ABSTRACT FROM AUTHOR]

Ion implantation effects at \SiO2/\SiC and \Al2\O3/\break\SiC interfaces have been investigated by implanting Ar ions at the interface of oxide and SiC. Capacitance–voltage relation and breakdown properties for these dielectrics are studied before and after implantation. The results indicate that the \SiO2/\SiC interface is sensitive to ion fluences higher than \1 \times \10^11\ \cm^-2, while \Al2\O3 on SiC can sustain higher fluences. In addition, the breakdown of the \Al2\O3 is found to be less sensitive to the ion implantation. [ABSTRACT FROM AUTHOR]