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The power electronics industry is now facing the higher power density design challenge to keep size shrunken but still meet the strict requirement for electromagnetic compatibility regulation. In this study, we investigated the conducted emission from a high-efficiency and compact size ac-dc switching power adaptor with flyback converter topology, and analyzed the root cause of EMI problem to further apply mitigation techniques for achieving regulation compliance. We first performed conduction emission test to obtain the emission profile for later result comparison and validation, and then utilized the ANSYS Simplorer and Q3D simulation tools to establish the analysis model for the fly-back switching power adaptor. After the simulation of the power module model being validated for effectiveness, we finally implemented the filtering scheme and PCB layout modification to effectively reduce the conducted noise and meet the product standard requirement.

The micro-grid power system is a world-wide trend for green energy demanding as part of smart-grid, and the most popular solar-cell inverter is possible suffering the surge transient disturbance from connected power system. This study investigates the electromagnetic model establishment for surge transient immunity protection analysis with ANSYS simulation tool. We first verify the simulated output of surge generator meets the waveform requirement for IEC61 000-4-5, and then investigate the possible scheme for circuit protection with proper TVS devices and placement location. We also try to investigate the possible intruding surge monitoring mechanism by analyzing the spectrum characteristics via coupling device for power system alarm implementation.

It is a challenge to predict the long-term future data from time series data. This paper proposes to use a Transformer with soft dynamic time wrapping for early stopping criteria, called a soft-DTW Transformer. Our experiment in an open-source dataset HouseTwenty shows that the average prediction error rate with soft-DTW Transformer is 27.79%, greatly reduced from 45.70% for using SVR, a common time series method.

This paper describes the utilization of ANSYS Designer with measurement validation to provide tool for analyzing, predicting and optimizing the EFT Burst transient noise suppression implementation and effectiveness to meet the requirement of IEC61000-4-4 [1] (EFT/B). In addition, the paper describes how electromagnetic simulations can provide chip-level immunity analysis for IEC 62215-3 [2]. The analysis of residual transient noise energy from transient noise suppressing devices can also provide significant benefits to EMS protection from chip, module, and all the way to board and system level. This study intends to provide an efficient simulation model to help electronic engineers enhancing their product design reliability.

With the development of IC nano-meter technologies advancing toward higher operating frequencies and the trend of integrated various wireless communication systems for smart autonomous car, the self-driving system with highly integrated high-speed digital circuits and multi-radio modules are now facing the challenge from performance degradation by even more complicated platform EMI noisy environment. Thus the radiated EMC problem has become a crucial issue for IC adoption by automobile industry. Since TEM Cell could be used for EMI test (IEC 61967-2[1]) and EMS test (IEC 62132-2[2]) on chip or module level, we therefore design and investigate the structure of TEM cell and its characteristics for IC EMC test in this study. Finally, we will utilize the TEM cell designed in this study to measure the EMI emission generated from flash memory under different operation and working conditions.

The trend of smart vehicle for ever increasing need on safe and comfortable driving environment, the more electronic equipment and electronic control unit (ECU) are implemented on automotive. Since the multi-purpose micro-controllers are widely adopted by automotive industry for advanced functional features, their EMI characteristics is crucial for safety issue because of possibly degraded communication signal due to EMI noise. There are also increasing RFI problem resulting from high-speed digital devices interfering wireless communication module on board. We therefore will investigate the EMI and RFI phenomena of micro-controller under different clock frequencies and operating voltages in this study. We will utilize the chip level EMI measurement methods IEC 61967-2[1] and IEC 61967-3[2] with self-designed high-sensitivity near-field probe. With the measured results and related EMI data analyzed, we can establish the EMI list of micro-controller and provide design reference for automotive electronics meeting EMI compliance requirement.

This work presents an Ultra-wideband (UWB) indoor positioning system for tracking customer pathway. The position is located by the triangulation method and the Gauss-Newton method is utilized to ameliorate the location accuracy. Experimental results indicate that the Gauss-Newton method decreases the measured positioning errors at different distances. Consequently, this indoor positioning system can provide a high precision positioning performance in tracking customer pathway and determine which commodity is the nearest one to the customers.

Since system level ESD testing is today applied to a wider range of products than ever before. Designing ESD robust systems can be very challenging, especially for systems which integrate advanced technology integrated circuit (IC) components. Solving ESD problems can lead to other complications on layout of chip and board level with verification. Since the ESD stress current makes its own path from injection spot to pins of IC under test or adjacent metal parts, such as trace or ground, we need to investigate those possible current paths forming a propagating chain on PCB of mounted component devices. A key finding of ESD design for sensitive IC mounted PCB is the analysis of the stress reaching IC / module/system level circuit so that best practice ESD protection and controls can be achieved. In this paper, we investigate the effect of different return paths on various ground plane configurations on board level ESD problem with the utilization of ESD generator model previously validated.

The DC-DC converter is a crucial component of electronic modules or systems, and thus making electromagnetic interference issue essential. Even though power IC manufacturer often provides useful PCB design guidelines, but power electronic engineer sometimes ignores the design rules because of his own application concerned or cost issue. This usually leads the converter to a poor EMI performance in the first time, thus requiring additional engineering resources, greater time to market, as well as higher EMI filter costs to comply with related EMI regulations. In this paper, we'll analyze the root cause of EMI problem on a DC-DC converter module built with single layer-double side PCB, and point out some factors of PCB ground design that will affect the EMI performance. Since there is no complete pair for power-ground plane, the plane resonance issue will not be discussed in this paper.

There is a growing awareness in the electronics manufacturer that system level ESD robustness is an important requirement for reliable products. System level ESD testing is today applied to a wider range of products than ever before. Designing ESD robust systems can be very challenging, especially for systems which integrate advanced technology integrated circuit (IC) components. While IC level ESD design and the necessary protection levels are well understood with reliability test from CDM or HBM model, system ESD protection strategy and design efficiency have only been dealt with in an ad hoc manner. We wish to explore realistic system or chip ESD protection requirements and strategies for normal operating IC chip or system, and therefore we have to establish the realistic ESD generator model to be incorporated with chip or system under investigation. Many of the most severe system level ESD design problems can be then traced to the affected location of system or chip with analyzing the residual ESD stress after injection and propagation. With this help, we can then adopt a consolidated approach to system level ESD design, and validate future success in building ESD robust systems through simulation in advance.

In this paper, we proposed a novel test compaction algorithm, called Parallel Order Dynamic Test Compaction (PO-DTC). We show that the order of secondary faults within a single test generation is important for test compaction. We launch parallel ATPG with different orders of secondary faults and choose the best test pattern with the largest number of detected faults. Experimental results show that our test length is 48% shorter than that of a highly compacted commercial ATPG. Our test length is the smallest among all previous work published so far. Our test length for N-detect test sets is at least 1/4 shorter than that of the commercial ATPG.

Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional path delay fault ATPG is not sufficient for hold-time faults. A hold-time fault ATPG is presented to generate robust test patterns. Experiments on large benchmark show that our test patterns are 42% shorter while 38% better in robust fault coverage than 1-detect stuck-at fault test sets. The results justify the need for hold-time fault ATPG.

A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.

Sputtering from a single CIGS compound target is a promising process to fabricate CIGS absorbers for mass production. However, only few reports demonstrate efficient CIGS cells without post-selenization. The need for the additional post-selenization step may be possibly due to the low Se supply during deposition, which originates from the low Se content in the target. In this study, we proposed a method to supply extra Se, sputtering from a Se target. With this, the Se supply during the quaternary sputtering process is adjusted nominally from 1 to 1.24. The effects of Se supply during the quaternary sputtering process on the film and device properties were studied. Efficiency of 11% was obtained with medium Se flux.

In this study, we have obtained uniform and high quality Cu2ZnSnS4 (CZTS) nanocrystals which were synthesized by using the hot injection method. The effect of injection rate on growth mechanism was investigated. The injection rates were varied from 2.5 to 20mL/h. The CZTS nanocrystals were characterized by TEM, XRD, and Raman. The Raman spectrum revealed good crystallinity, and TEM images showed uniform dispersion. As the injection rates increased, the CZTS particles size become larger and less uniform, which was consistent with LaMer model. The composition of CZTS nanocrystals was almost close to stoichiometry, and we obtained the CZTS nanoparticles with good crystallinity for the case injected at 10mL/h.

The most high efficiency cadmium-free CIGS solar cell is zinc sulfide fabricated by chemical bath deposition. However, on account of the presence of Zn(OH)2 phase during chemical reaction, it leads to poor cell performance attributed in low fill factor and shows distorted I-V curve. The cell performance can be enhanced by continuous illumination, which has been found by many groups called light-soaking effect. In this paper, we compared two different chemical processes with and without ammonia hydroxide etching. The well-known ammonia etching effect for removing Zn(OH)2 phase has also been observed in this work. By comparing the different chemical processes with ammonia etching, we noticed the difference of compositions due to chemical reaction routes. Based on the research for chemical routes, we further to optimize CBD-ZnS process deposited on CIGS substrates. Owing to the decrease of Zn(OH)2 concentration by optimized CBD-ZnS, the cell efficiency can be improved in Voc and FF. Moreover, the time for lightsoaking treatment can be shortened to less than 20 minutes.

In this work, selenium treatment at 250-350°C on the polycrystalline CuIn1-xGaxSe2 (CIGS) thin films sputtered from a quaternary target has been investigated in order to passivate anionic defects which induce the current-blocking behavior and lowering open circuit voltage. The CIGS thin films were selenized in a closed-space graphite container. The result of selenization was characterized by Raman spectroscopy, EQE and the current-voltage-temperature measurement. After selenization at 350°C, the current-blocking behavior is inhibited and Voc increases from 310mV to 640mV. Until now, the efficiency near 9% can be obtained by an optimized selenization process.

In this paper, a new pseudo-Gaussian-based compensatory neural fuzzy system (PGCNFS) is proposed. The characteristic of compensatory neural fuzzy system is building exact fuzzy reasoning and converging quickly. Besides, the pseudo-Gaussian membership function can provide the compensatory neural fuzzy system which owns a higher flexibility and can approach the optimized result more accurately. An on-line learning algorithm is proposed to automatically construct the PGCNFS. It consists of structure learning and parameter learning that would create adaptive fuzzy logic rules. Experimental results show that the proposed algorithm converges quickly and the obtained fuzzy rules are more precise.