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In view of the need to use multiple remote controls to operate separately when watching HDTV, in order to reduce the unnecessary operation of users in the process of viewing the film, HDMI-CEC is generated, which just meets the needs of users. At present, all HD(High-Definition Multimedia Interface) devices produced by manufacturers have CEC(consumer electronic control)function. CEC function brings a lot of convenience to users. It allows end users to control multiple HD devices with CEC by using one remote controller, thus reducing the number of remote controls. This design is a controller based on HDMI version. The Hardware Description Language Verilog is used to realize the design of CEC bus controller IP core. VCS simulation tool is used to verify the design. The experimental results show that the design meets the requirements of hdmi-cec bus controller design. This article mainly talks about HDMI-CEC protocol, design architecture, micro architecture, and software hardware coordination design method.

3D object detection based on point cloud data is an essential part of L4 automatic driving. This paper proposes a novel end-to-end trainable deep learning network structure, PPMGNet, which can quickly encode point clouds, obtain the spatial feature of point clouds, predict multiple categories, and perform 3D object detection in real time. A large number of experiments show that in terms of speed and accuracy, PPMGNet's detection performance is very suitable for direct deployment in autonomous driving applications.

In this paper, a new low temperature coefficient (TC) high power supply rejection ratio (PSRR) bandgap voltage reference is presented in CMOS technology. In order to achieve low TC and high PSRR voltage reference with small area overhead and good practicability, the proposed circuit uses a curvature correction method based on sub-threshold current and a PSRR enhancement circuit. When the power supply voltage is 3.3V, this circuit is devised and verified using 0.18pm CMOS process. The results show the output voltage is constant at 1.247V at room temperature. The output voltage range is 0.674 mV and TC is 3.029ppm/°C in a wide temperature range of -55°C to 125°C. The measured PSRR is 98.36dB at lKHz and more than -44.28 dB at 1MHz.

This article focuses on the design of a system-level verification platform for a static random-access memory (SRAM) module. The SRAM module is in a CAN-FD SOC chip. The SRAM memory controller verified by the verification platform in this paper is an important module integrated on the APB SOC chip bus for basic communication with CAN-FD IP. By adopting UVM universal verification methodology, a complete verification platform and verification environment suitable for the module are designed and built; by generating constrained random test excitation signals, the function of the controller is fully verified, and the results can be automatically compared with the data. The results show that the verification platform can greatly reduce the development time of verification incentives, simplify the verification process, shorten the verification cycle and have good reusability.

Based on the quick sorting algorithm, this paper uses verilog language to implement the RTL design of the ID sorting module applied to the CAN bus controller, and performs functional simulation on the module. Simulation results show that the ID sorting module designed in this paper can quickly sort up to 64 different ID numbers and output correct sequence to meet the design requirements. Using a parametric design strategy, the ID sorting module designed in this paper can configure parameters to achieve the function of sorting a larger number of random sequences to meet different needs, and has high scalability and practicality.

In this paper, we use Python script to read the function detailed description documents of CAN-FD IP, extract the required information according to the main keywords and other information, and automatically generate the qualified System Verilog constrained randomized register configuration stimulator. The simulation results show that the stimulator can meet the design requirements for the configuration of excitation, and can effectively improve the design efficiency of the verification platform.

CAN-FD bus protocol has a high effective data rate and is widely used in automobile internal bus. This paper introduces the design of CAN-FD protocol controller driver based on Cortex-M0 processor, analyzes the development process of CAN-FD driver in detail, realizes multi node communication by communicating with other CAN-FD nodes, and uses CAN-FD analyzer and logic analyzer to grasp the CAN-FD frame on the physical bus. Through the actual CAN-FD communication project, this paper completes the design process of the driven, and provides a reference value for the driven design of other CAN-FD devices.

This paper introduces the whole process of verifying the AHB-SRAM controller using UVM verification methodology, and expounds the verification function points, coverage statistics and final regression in the implementation process. The verification results show that the read and write functions of the AHB-SRAM controller under various conditions are correct and its coverage rate reaches 100% in the regression test. his paper is based on UVM verification method, which has high portability, improves the verification efficiency and meets the chip verification requirements.