1. Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm.
- Author
-
Liu, Mingshan, Scholz, Stefan, Hardtdegen, Alexander, Bae, Jin Hee, Hartmann, Jean-Michel, Knoch, Joachim, Grutzmacher, Detlev, Buca, Dan, and Zhao, Qing-Tai
- Subjects
PLASMA etching ,DIAMETER ,SEMICONDUCTOR nanowires ,OHMIC contacts ,PASSIVATION ,NANOWIRES ,TRANSISTORS - Abstract
In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$. The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$. Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF