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Nuclear power plants (NPPs) are complex dynamic systems with multiple sensors and actuators. The presence of faults in the actuators and sensors can deteriorate the system’s performance and cause serious safety issues. This calls for the development of fault detection and diagnosis systems for detection and isolation of such faults. In this study, fault detection and diagnosis (FDD) based on neural networks (NN) and K-nearest neighbour (KNN) algorithm is applied to a pressurized water reactor (PWR). Fault detection is first determined based on the NN. Second, the KNN algorithm is used to classify the faults. The proposed approach is capable of classifying a variety of actuator faults, sensor faults, and multiple simultaneous actuator and sensor faults. A set of simulation results is provided to demonstrate the accuracy of the FDD method. The classifier performance is further compared with other machine learning techniques.

This paper proposes an interleaved high step-up DC-DC converter with the coupled inductor (CI) and built-in transformer (BIT) for renewable energy applications. Two double-winding (2W) CIs and one triple-winding (3W) BIT are integrated with the switched-capacitor (SC) voltage multiplier cells (VMCs) to achieve high-voltage gains without extreme duty cycles. The CIs and BIT turns-ratios provide two other degrees of freedom—in addition to the duty cycle—to adjust the voltage gain that leads to increased design flexibility. The diodes turn off naturally under the zero-current switching (ZCS) conditions because their current falling rates are controlled by the leakage inductances of the CIs and BIT; therefore, the diodes’ reverse-recovery problems are alleviated. Moreover, employing passive diode-capacitor clamp circuits, the voltage stresses of the switches are limited to a low value far less than the output voltage. Additionally, the leakage inductances energies are recycled and transferred to the output to further extend the voltage gain. Furthermore, due to the interleaved structure, the input current ripple and current stresses of the components are reduced. The proposed converter is analyzed in detail and then compared with similar converters that employed CIs and/or BIT along with passive/active clamp circuits for the MOSFETs. Finally, to verify the feasibility of the proposed converter, the experimental results of a 200 W prototype with output voltage of 400 V and voltage gain of 25 are presented.

This paper presents a new low-voltage CMOS structure for operational transconductance amplifier (OTA) exploiting the bulk-driven, the self-cascode and the multiple-input transistor techniques (MI). The multiple-input OTA (MIOTA) circuit operates in subthreshold region using 0.5V supply voltage and offers enhanced linearity. The MIOTA is developed for biopotential signal as well as electrocardiogram (ECG) signal processing circuit and it is exploited to design a 5th-order Chebyshev low-pass and 3rd-order band-pass filters with a dynamic range (DR) of 57.6 dB and 60.4 dB, and nanopower consumption of 50 nW and 60 nW, respectively. Due to the electronic tuning of cut-off frequency, the low-pass and band-pass filters are suitable for random noise and motion artifact noise reductions in biopotential signals. The circuits were designed in Cadence environment using the standard N-well $0.18~\mu \text{m}$ TSMC CMOS technology. Intensive post-layout simulation results along with the process, voltage, temperature analysis (PVT) and Monte Carlo (MC) prove the robustness of the design. The chip area of the proposed MIOTA is 0.00725 mm2 ( $118~\mu \text{m}\,\,\times 61.5\,\,\mu \text{m}$ ). Compared with standard OTA the MIOTA offers simplification of filter topology and reduced number of active elements. In order to demonstrate these advantages, the MIOTA-based filter was also build using commercially available OTA LT1228. The experimental results of OTA LT1228 confirm both the filter functionality and the advantages of the proposed MIOTA.

Stanford memristor model is a widely used model that accurately characterizes real non-volatile metal-oxide resistive random access memory (RRAM) devices with bipolar switching characteristics. The paper studies for the first time the dynamics and bifurcations in a class of nonlinear oscillators with real non-volatile memristor devices obeying Stanford model. This is in contrast with papers in the literature considering oscillators with ideal, abstract, or artificial memristor models, that are unable to describe physical memristors implemented in nanotechnology. One main new idea in the paper is to use the memristor as a programmable nonlinear resistor. Namely, two principal modes of operation are considered. 1) Analogue transient phase: the oscillator is designed so that in the transient oscillations the voltage on the memristor is below threshold, hence the main memristor state variable, i.e., the gap of the insulating material, is almost constant and the memristor behaves as a static nonlinear resistor. 2) Programming phase: the nonlinear characteristic of the memristor, which depends on the gap, can be changed via the application of voltages above threshold. The paper studies nonlinear oscillations in the transient phase for a fixed gap as well as the bifurcations phenomena displayed when the gap is varied. The paper also discusses the differences between the approach in the paper and those to design other memristor oscillators with non-volatile memristors.

We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL) current in erase operation of FeFETs with a floating body. We also introduced a novel gate stack process for low voltage operation by inserting a Ti layer in the metal gate. The Ti layer insertion can suppress the growth of an interfacial layer (IL) by controlling oxygen intrusion into the IL during the rapid thermal anneal (RTA) process. We demonstrated an efficient erase operation at shorter and lower pulse voltage with GIDL current in the overlap structure than in the underlap structure. A compact FeFET retention model is developed based on the surface-potential based FET model, the nucleation-limited-switching (NLS) model, and the retention model of ferroelectric (FE) capacitor. Faster degradation of the program state observed in the experiment can be explained by electron detrapping according to the modeling and simulation.

In this paper, the analysis and simulation of shunt reactor turn-to-turn faults, as well as the algorithms for their detection, are presented. A simple equivalent circuit of a shunt reactor applicable for a small number of short-circuited turns was developed and applied to simulate such faults. It is shown why the commonly applied differential relays are not able to detect turn-to-turn faults. Then three new algorithms are introduced, and their performance is analyzed for simulated internal faults. The proposed methods are based on zero-sequence reactance, negative-sequence reactance, and phase impedance. The sensitivity and security of the presented methods are discussed. The proposed algorithms’ performance has been tested with the signals generated with the use of the MATLAB/Simulink program. The results confirm that the proposed algorithm can effectively improve the detection of turn-to-turn faults. The paper ends with recommendations for the setting of the proposed protection schemes.

In this letter, an alternative solution for travelling wave based directional relaying scheme is presented by utilizing the prefault voltage sample acquired at a much lower sampling rate along with current travelling wave. There is no requirement of voltage travelling waves for the method. The performance of the proposed method is evaluated for faults simulated on a 400 kV transmission network which reveals its advantage for faults when change in voltage signal is low. The proposed method is independent of the transient response of the capacitive voltage transformer.

This paper discusses a method for accurately estimating the fault location in multi-terminal High Voltage direct current (HVdc) transmission network using single ended current and voltage measurements. The post-fault voltage and current signatures are a function of multiple factors and thus accurately locating faults on a multi-terminal network is challenging. We discuss a novel data-driven Bayes Regression based method for accurately predicting fault locations. The sensitivity of the proposed algorithm to measurement noise, fault location, resistance and current limiting inductance are performed on a radial three-terminal MTdc network. The test system is designed in Power System Computer Aided Design (PSCAD)/Electromagnetic Transients including dc (EMTdc)., Comment: arXiv admin note: text overlap with arXiv:2201.08263

Quantum computing is a new technology that is expected to revolutionize the computation paradigm in the next few years. Qubits exploit the quantum physics proprieties to increase the parallelism and speed of computation. Unfortunately, besides being intrinsically noisy, qubits have also been shown to be highly susceptible to external sources of faults, such as ionizing radiation. The latest discoveries highlight a much higher radiation sensitivity of qubits than traditional transistors and identify a much more complex fault model than bit-flip. We propose a framework to identify the quantum circuits sensitivity to radiation-induced faults and the probability for a fault in a qubit to propagate to the output. Based on the latest studies and radiation experiments performed on real quantum machines, we model the transient faults in a qubit as a phase shift with a parametrized magnitude. Additionally, our framework can inject multiple qubit faults, tuning the phase shift magnitude based on the proximity of the qubit to the particle strike location. As we show in the paper, the proposed fault injector is highly flexible, and it can be used on both quantum circuit simulators and real quantum machines. We report the finding of more than 285M injections on the Qiskit simulator and 53K injections on real IBM machines. We consider three quantum algorithms and identify the faults and qubits that are more likely to impact the output. We also consider the fault propagation dependence on the circuit scale, showing that the reliability profile for some quantum algorithms is scale-dependent, with increased impact from radiation-induced faults as we increase the number of qubits. Finally, we also consider multi qubits faults, showing that they are much more critical than single faults. The fault injector and the data presented in this paper are available in a public repository to allow further analysis., 13 pages, 11 figures. To be published in the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'22)

RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and precharging a DRAM row, and thus alternating the voltage of a row's wordline between low and high voltage levels, can cause bit flips in physically nearby rows. Recent DRAM chips are more vulnerable to RowHammer: with technology node scaling, the minimum number of activate-precharge cycles to induce a RowHammer bit flip reduces and the RowHammer bit error rate increases. Therefore, it is critical to develop effective and scalable approaches to protect modern DRAM systems against RowHammer. To enable such solutions, it is essential to develop a deeper understanding of the RowHammer vulnerability of modern DRAM chips. However, even though the voltage toggling on a wordline is a key determinant of RowHammer vulnerability, no prior work experimentally demonstrates the effect of wordline voltage (VPP) on the RowHammer vulnerability. Our work closes this gap in understanding. This is the first work to experimentally demonstrate on 272 real DRAM chips that lowering VPP reduces a DRAM chip's RowHammer vulnerability. We show that lowering VPP 1) increases the number of activate-precharge cycles needed to induce a RowHammer bit flip by up to 85.8% with an average of 7.4% across all tested chips and 2) decreases the RowHammer bit error rate by up to 66.9% with an average of 15.2% across all tested chips. At the same time, reducing VPP marginally worsens a DRAM cell's access latency, charge restoration, and data retention time within the guardbands of system-level nominal timing parameters for 208 out of 272 tested chips. We conclude that reducing VPP is a promising strategy for reducing a DRAM chip's RowHammer vulnerability without requiring modifications to DRAM chips., To appear in DSN 2022

By using a single dc voltage source to feed a 4-level switched-capacitor (SC) unit and a 3-level NPP/NPC unit simultaneously, a new 9-level inverter is developed in this work. The 4-level unit is implemented by cascading an inverting half-bridge with a double- or half-mode SC circuit. It involves four transistors, two diodes and two capacitors with self-balanced voltage. Inrush charging current variation di/dt of capacitors at switching instants is successfully suppressed by inserting a small inductor into the SC unit. Compared with the existing solutions for 9-level inverters, the proposed circuit has the advantages of simpler structure and lower cost per level. These make the proposed inverter very suitable for low voltage applications such as PV and fuel cells. Circuit configuration, operation, system characteristics under POD-PWM modulation are analyzed in detail. Feasibility and dynamic performance are also demonstrated experimentally.

The submodule capacitor voltage fluctuation of the modular multilevel converter (MMC) leads to the increase of the size of the submodule capacitor, the increase of system cost, and the decrease of system reliability and stability. In order to solve the problem, the mathematical model of circulating current voltage drop is derived, and the mechanism of circulating current on the submodule capacitor voltage fluctuation is studied through the submodule switching function. A control strategy for suppressing the submodule capacitor voltage fluctuation is proposed, which is based on circulating current voltage drop balance (CCVDB). The simulation model is built to compare three control strategies for suppressing submodule capacitor voltage fluctuation under the step changes of DC bus voltage and active power, namely, the circulating current is suppressed to zero, the second-order component of the submodule capacitor voltage is suppressed to zero, and the CCVDB strategy. The research results show that the CCVDB strategy can effectively suppress the submodule capacitor voltage fluctuation, reduce the capacitance demand, and reduce the total harmonic distortion (THD) of the submodule capacitor voltage, which verifies the feasibility and effectiveness of the CCVDB strategy.

Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs enable communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing in which hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router’s local core. Such a utilization-centric design approach can raise security issues in NoC-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

Gallium nitride high electron mobility transistor (GaN HEMT) is liable to gate false turn-on problem when the gate crosstalk voltage exceeds its threshold voltage in the widely adopted phase-leg topology due to its low threshold voltage and high switching speed. Without considering the gate loop stray inductance, gate internal resistance, nonlinearity of parasitic capacitances and power loop stray parameters, traditional false turn-on analytical method is insufficient to support accurate analysis. And it has been found that GaN HEMT gate-source parasitic capacitance $C_{\mathrm {gs}}$ previously assumed constant is otherwise highly nonlinear and has strong impacts on the gate crosstalk voltage. This paper has measured $C_{\mathrm {gs}}$ by vector network analyzer and constructed an accurate nonlinear model of $C_{\mathrm {gs}}$ , based on which an accurate GaN HEMT behavior model is further fulfilled. The accuracy of the proposed behavior model has been verified by large amounts of experiment results. The proposed GaN HEMT model is used to accurately calculate gate crosstalk voltage and switching losses. Besides, false turn-on induced extra loss has been calculated and is adopted as a criterion to evaluate the severity of false turn-on and optimal design method for false turn-on suppression has been detailed further.

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness ( $t_{FE}$ ) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a $14nm$ FDSOI technology node, exploring the impact of $t_{FE}$ on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., $I_{ON}$ , $SS$ , $I_{ON}/I_{OFF}$ and $C_{gg}$ ) by varying $t_{FE}$ up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum $t_{FE}$ . We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum $t_{FE}$ . Further, we analyze the impact of $t_{FE}$ on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with $t_{FE}$ . However, the WNM in general follows a non monotonic trend w.r.t $t_{FE}$ , and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized.

The modular and voltage scalable features of modular structure based power converter has attracted for wide power range applications. However, balancing the capacitor voltage becomes complex when the number of sub modules is increased. In a conventional system, for balancing a capacitor voltage, separate monitoring and control are required for each sub module, which further increases the cost and burden to the converter. This paper proposes a simplified logical method (SLM) for balancing the capacitor voltage of each sub module without any additional sensors and controllers. The capacitor voltage of N sub modules is balanced based on the simple logical function, which eventually balances the capacitor voltage and thus reduces the voltage ripple of each capacitor. In addition, this method suppresses the circulating current and common mode voltage, which increases the efficiency and cost effective of the converter. The level shifted carrier technique is used for providing desired pulse signals for the switching devices in the converter. The effective performances of the proposed method are validated using simulation and experimental setup.

Scan chain diagnosis is essential to solving yield-reduction problem caused by the miniaturization of manufacturing process. The accurate diagnosis of scan chain faults that frequently occur in the initial process is vital for rapidly improving yield. Moreover, the importance of scan chain diagnosis with a high resolution for the multiple faults is increasing because multiple faults occur in the early stages of the process, further increasing the cost of physical failure analysis. Although multiple faults can be diagnosed with existing methods, a high diagnostic resolution is difficult to achieve in the early stages of the process (where many faults occur) due to the rapid increase in the number of diagnosed fault candidates as the number of actual faults in the circuit increases. In this paper, a novel reconfigurable scan architecture that reconfigures the diagnosis paths and a test algorithm that uses this scan architecture are proposed to reduce the number of diagnosed fault candidates in the scan chain diagnosis with multiple circuit faults. Experimental results indicate that the proposed method achieves the higher diagnostic resolution for multiple faults than conventional methods. In addition, the proposed method reduces the routing overhead by scan partitioning.

The voltage rating of commercial Gallium Nitride (GaN) power semiconductors is limited to 600/650 V because of the lateral structure. Stacking low-voltage switches is an effective way to block higher dc-link voltage. However, unbalanced voltage sharing can occur even with well-matched gate drivers and semiconductors due to the device-to-ground displacement currents. As a result, the low-voltage switches may suffer from over-voltage breakdown. This study presents a novel closed-loop current source gate driver to address the unbalanced dynamic voltage sharing issue. Additional compensation current is actively injected into the switch gate to counteract the voltage imbalance brought by the device-to-ground displacement currents. Compared with the conventional voltage source gate driver-based active gate control method, the proposed current source gate driver tunes the switch turn-off timing and dv/dt more accurately because the switch gate current is directly regulated. Meanwhile, since both the pulse width and amplitude of the compensation gate current can be adjusted, the proposed active gate control is more flexible for adapting to different operating conditions. Moreover, without employing snubber circuits or extra Miller capacitors, the switching speed and switching energy of the GaN devices are not compromised. By implementing the proposed gate driver and voltage balancing schemes, well-balanced voltage sharing can be obtained for both soft-switching and hard-switching scenarios. A series-connected GaN-based multiple pulse tester (MPT) is built to prove the effectiveness of the proposed approach under different load and different switching speed (dv/dt) conditions.

Traditional in-Silicon PN-junction-based on-chip electrostatic discharge (ESD) protection structures have inherent ESD-induced design overhead problems, including parasitic capacitance, leakage and Si area consumption. A potential solution to the ESD design overhead challenge is to use a non-conventional above-Si graphene-based nano-electrical mechanical system (gNEMS) transient switch structure to protect integrated circuits (ICs) against ESD failures. This paper reports investigation of materials and device structural impacts on gNEMS ESD protection structures. Transmission-line pulse (TLP) testing confirms that single-crystalline graphene gNEMS switch achieves a record high ESD current-handling capability of $\text{J}_{t2} {\mathbf {\sim }} 1.03\boldsymbol {\times } 10^{9}\text{A}$ /cm2, at least four times higher than $\text{J}_{t2} {\mathbf {\sim }} 0.24\boldsymbol {\times } 10^{9}\text{A}$ /cm2 for its poly-crystalline graphene counterpart. Transient 3D finite element method (FEM) simulation reveals that both device dimensions and shapes of the suspended graphene membranes can substantially affect gNEMS ESD discharging characteristics. The discovery offers guidelines for design optimization of gNEMS ESD switch structures.

Power system transient stability assessment (TSA) and control is a complex problem. TSA from the perspective of individual machine Kimbark curves forms a distinctive approach. On the other hand, transient stability constrained optimal power flow (TSC-OPF) has been adopted widely for determining preventive control actions against transient instabilities under a given contingency. This paper presents a strategy for transient stability control, which mainly integrates the concepts of individual machine methods based TSA and global TSC-OPF. The proposed workflow is mainly based on the most severely disturbed machines (MDM) and their critical trajectories. These are utilized in deciding the number of TSC-OPF transient stability constraints, the minimum upper time limit for TSC-OPF solution interval, and security-based transient stability constraint of individual machines. Further, the application of the proposed method is explained with respect to stabilization of three different transient instability scenarios viz., transient instability originates from first swing instability, transient instability originates from multi swing instability but leads to first swing instability as fault duration increases, and transient instability originates from multi swing instability, but never leads to first swing instability as fault duration increases. IEEE 39 bus and 118 bus test system are considered for testing the proposed control strategy. The proposed approach, which expresses the transient stability constraints in global TSC-OPF in terms of some selective machine (i.e MDMs) critical trajectories not only forms a distinctive approach but also provide a smooth reconciliation between economy of operation and security level while ensuring transient stability under a given contingency.

Large-size TSVs have larger parasitic capacitance, which leads to more resolution challenges. At the same time, due to the opposite fault effect of resistive open fault and leakage fault in the ring oscillator, the coexistence of two types of faults will cause serious test confusion. These problems significantly increase the difficulty in the TSV test. In this paper, a test method using Schmitt trigger as a TSV receiver is presented to enhance test resolution and reduce test confusion when two kinds of faults exist simultaneously. Schmitt trigger that is characterized by two threshold voltages is used to improve the test resolution. By reducing the supply voltage and checking whether the ring oscillator oscillates, we can identify whether there are two kinds of faults coexisting. HSPICE simulation results based on $45~nm$ CMOS technology demonstrate that the proposed method offers better test resolution in terms of large-size TSVs compared with the existing similar methods, and can distinguish the misdiagnosis when there are two kinds of faults existing simultaneously in a TSV.

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky barrier (SB) FinFETs for sub-10-nm gate length. The study has three subsections. First, two-transistor (2T) and 4T and-or-invert (AOI)/or-and-invert (OAI) gates with select bits that allow multiple logic functions are introduced. Second, the use of WFE to create ultracompact reconfigurable logic circuits of fundamental operations (0, 1, OR, AND, NAND, NOR, and XOR) are explored via novel 2T, 3T, and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multistage circuits, such as compact full adders, are also modeled via TCAD simulations. Power $\times $ delay product (PDP) figures and dc gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact 1-bit arithmetic logic unit (ALU), which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, addition, and subtraction) with three select bits using only 26 SB-FinFETs, saving a substantial amount of power and chip area. The tradeoffs between the number of metal work-functions used in the designs, circuit complexity, and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET-based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using $\times 3$ to $\times 10$ less power and between $\times 2$ and $\times 15$ less area than static CMOS counterparts. Although they suffer greater delays ( $\times 2$ – $\times 5$ ), the overall PDP performance remains comparable to conventional CMOS.

This work presents and analyses the design of a multi-mode Low Noise Amplifier (LNA) dedicated to 2.4 GHz Wireless Sensor Network (WSN) applications. The proposed inductorless LNA, implemented in a 28 nm FDSOI CMOS technology, is based on a common-gate configuration imbedded with a common-source stage to boost the overall transconductance of the circuit. The LNA is specifically designed, and optimized, to address three modes of operation. The reconfiguration is performed through current tuning, combined with switching the back gate of the amplification transistors. The proposed implementation allows the figure of merit (FOM) to be maintained constant in the different modes of operation. In the low power mode, the LNA only consumes 350 uW. It achieves a voltage gain ( $\text{G}_{\mathrm {v}}$ ) of 16.8 dB and a noise figure (NF) of 6.6 dB. In the medium performance mode, the gain and the NF are respectively improved to 19.4 dB and 5.4 dB, the power consumption is 0.9 mW. In the high-performance mode, the gain is maximum, 22.9 dB, and the noise figure is minimum, 3.6 dB, for a power consumption of 2 mW. The linearity represented by the input referred third-order intercept point (IIP3) is constant, close to −16 dBm. The reported LNA occupies only 0.0015 mm2.

Hardware cybersecurity has become a key issue, especially for very large integrated circuits. If counterfeit, forged, or defective ICs present a significant threat to system reliability and security. The growing complexity of digital and mixed-signal systems makes it increasingly challenging yet vital to develop robust methods to assess and confirm the reliability and authenticity of ICs. We introduce a new terahertz testing method for non-destructive and unobtrusive identification of counterfeit, damaged, forged or defective ICs by measuring their response to incident terahertz and sub-terahertz radiation at the circuit pins and analyzing the response using artificial intelligence (AI). These responses create unique signatures for ICs. We generated 2D images by measuring the response on a selected pin of a radio frequency IC (RFIC) scanned by a focused terahertz radiation. By applying the data augmentation processes, we created a secure image data set to train the convolutional neural network (CNN) model. An unsecured image data set representing altered or damaged ICs was generated by modifying the original image data. The trained models identified secure devices with a ~94% accuracy.

To prevent the passengers from electric shock, the DC-bus capacitor voltage of the high-voltage permanent magnet synchronous machine (PMSM)-based drives in electric vehicles (EVs) is required to decline to safe voltage as quickly as possible when emergency occurs. Considering that the discharge time for small safe current limit powertrain systems will be longer than required, this paper proposed a maximum power discharge strategy to accelerate the dissipating process and meanwhile avoid the voltage surge. Firstly, the PMSM discharge model as a generator is established on the basis of analyzing the discharge course. Secondly, the feasible reference current trajectory is presented by drawing the trajectories of the voltage, current, and power constraints. Then the maximum power discharge strategy is achieved by following the extreme points in the reference trajectory. Finally, simulation and experiment are conducted on a three-phase SPMSM powertrain system to validate the proposed algorithm can effectively shorten the discharge process.

A discrete GaN power transistor’s substrate is typically connected to its source electrode. However, on the GaN-on-Si power IC platform, the high-side transistor (HS-transistor) and low-side transistor (LS-transistor) share a common substrate that cannot be simultaneously connected to both source electrodes of the two transistors. Thus, the termination of the common substrate remains an undecided issue. In this work, comprehensive TCAD simulations are exploited to reveal the influences of various substrate termination schemes. It is found the common substrate inevitably leads to severe degradation in the dynamic ${R} _{\mathrm{ ON}}$ due to back-gating effects. The mechanisms for the degradations vary with the substrate termination scheme, and will be discussed in detail. To address these issues, we propose a new GaN power IC platform on an engineered bulk silicon substrate, and study the new platform with TCAD simulations. The proposed platform provides a local electrical substrate (a p+ island) for each GaN power transistor. The source electrode of each GaN transistor is connected to its local electrical substrate, while all devices share a common mechanical substrate. The junctions between the local substrates and the underlying n-layer provide an effective isolation between GaN transistors. The back-gating effects are completely suppressed for the GaN integrated bridge circuit.

To estimate characteristic fluctuation of emerging devices, three-dimensional device simulation has been performed intensively for various random cases; however, it strongly relies on huge computational resources. In this paper, we report a nanosized-metal-grain pattern-dependent model by using the method of multi-variable non-linear regression (MVNLR) for the threshold voltage fluctuation ( $\sigma \text{V}_{\mathrm {th}}$ ) of gate-all-around silicon nanowire metal-oxide-semiconductor field-effect transistors. The model is developed by perturbing the local metal grains of specific patterns and summing up each metal grain of various grain patterns. The method of MVNLR is applied to build equations for nominal devices, and devices with high work-function (WK) and low WK with respect to process parameters (radius of channel, gate length, channel doping, and oxide thickness), which are generated by the design of experiments. The proposed model can estimate the magnitude of $\sigma \text{V}_{\mathrm {th}}$ accurately (error rate < 1%) for all parameters, where an error-correction process is further adopted by using a simplified one-perceptron method.

This paper presents a low-voltage nano-power multiple-input operational transconductance amplifier (MI-OTA) with high linearity performance and increased input voltage swing. The enhanced performances are achieved thanks to employing several techniques as the bulk-driven, source-degeneration, self-cascode and negative conductance along with the concept of the input signal attenuation formed by multiple-input MOS transistor. The MI-OTA is widely tunable that serves for biological signals processing. A 3rd-order Butterworth band-pass filter (BPF) for electrocardiogram (ECG) signal processing with 55.8 dB dynamic rang is presented. The MI-OTA circuit is designed for 0.5V voltage supply and offers a 0.22% total harmonic distortion (THD) for 0.2Vpp input signal with total power consumption of 13.4nW. Extensive simulation results including Monte Carlo analysis and process, voltage, temperature (PVT) corners using the $0.18\mu \text{m}$ CMOS technology from TSMC confirm the characteristics of the proposed MI-OTA and the filter.

In high-temperature reverse-bias test of an insulated-gate bipolar transistor module, the problem of self-heating in chip resulting from power loss arises with high frequency. To address this problem, the law of the variation in leakage current with temperature for the reverse-bias state of a device is derived and utilized to establish a temperature calibration curve, with which the online measurement of the insulate-gate bipolar transistor module chip temperature can be implemented directly by real-time monitoring of device leakage current in high-temperature reverse-bias test. The method we proposed solves the problem of large measurement error in chip temperature obtained by traditional thermal resistance calculation method. In addition, real-time chip temperature can be monitored without introducing additional test circuit or HTRB interruption experiment. To demonstrate the effectiveness of the proposed method, the switching small-current temperature measurement method is used to make comparison, and the experiment result indicates that the temperature of the chip in the blocking test can be obtained with high precision by using the leakage current measurement method presented in this work.

Insulated gate bipolar transistor (IGBT) is widely used in power equipment, it generally works in complex circuit profiles and it is very difficult to measure or predict the thermal parameters of the module in real-time and evaluate the corresponding health status in the transient process. This paper develops a novel approach for solder-layer condition monitoring of IGBTs. In the approach a time-series nonparametric model of a power module is constructed, the current power and ambient temperature data are used to deduce the health state junction and case temperature. Three groups of time-series insulated gate bipolar transistors (IGBTs) data are used to train and verify the time-series nonparametric model for online conditions, the results show that the developed method has high accuracy. Compared with traditional methods, the time series non-parametric model method not only saves characteristic experiments but also saves the process of mathematical model construction. Besides, the proposed method also has the advantages of strong generalization and low equipment requirements which is useful for actual working conditions. Thereafter, another nonparametric model is built, the predicted junction temperature is used to estimate the collector voltage in the health state, and the percentage deviation of the measured collector voltage from the estimated voltage is used to do the state-of-health estimation of the IGBT and its accuracy is verified by the experiment result.

A digital true random number generator based on the oscillator phase generated by the second-order sub-harmonic injection locking phenomenon is proposed in this paper. Owing to the thermal jitter, the phase difference between a free-running (i.e., unsynchronized) oscillator and an injected external signal collapses to one of two stable solutions in a truly random manner. The injected external signal is generated from another oscillator operating at close to twice the frequency of the free-running oscillator. The random sequence extracted from the resulting stable solutions is bias- and correlation-free, nullifying the need for a bias compensation circuitry. The proposed design is demonstrated with extensive simulations to be robust under process, voltage, and temperature variations. The generated random patterns pass the National Institute of Standards and Technology test suite.

To improve the operation performance and energy conversion efficiency of the redox flow battery (RFB), a modular active balancing circuit for redox flow battery applied in the energy storage system is proposed in this paper. Detailed topology description, parameter design, characteristic analysis, operation principle and control strategy of the proposed circuit are presented and discussed in the paper. Different from the conventional battery balancing circuit, the key point of the proposed balancing circuit is that it integrates the circulating pump driving circuit and the state-of-charge (SOC) equalization circuit of the redox flow battery. It uses the energy consumption of the pump driving to balance the SOCs of different battery stacks, which provides a new SOC balancing mechanism for RFB. Based on the proposed circuit, an active balancing control strategy using the time-sharing energy transmission method is proposed, in which the sub-modules of the circuit are alternatively configured in charge-state and discharge-state for absorbing energy or releasing energy to achieve the SOC balancing control for RFB. Compared with the conventional balancing solution or circuit, the proposed modular active balancing circuit simplifies the complexity of the battery management system for RFB, which has the advantages of high efficiency, high reliability, and good scalability. Simulations on Matlab/Simulink and experiments on a downscaled prototype were carried out to verify the feasibility and effectiveness of the proposed circuit and control strategy.

This paper proposes a time-domain analog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the time domain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.

Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental conditions, such as high temperatures. Ensuring the reliability of microelectronic components is a major challenge at these high temperatures. The computing systems of these applications rely on DRAMs as working memory, which are built upon bit cells that store charges in capacitors. These commodity DRAMs are optimized for cost per bit and not for high reliability. Thus, very high temperatures impose an enormous challenge for commodity DRAMs as the data retention time and reliability decrease largely, affecting the data correctness. Data correctness can be ensured up to certain temperatures by increasing the refresh rate to counterbalance the retention time reduction. However, this severely degrades the access latencies and the usable DRAM bandwidth. To overcome these limitations, we present for the first time a Thermoelectric Cooling (TEC) solution for commodity DRAMs in harsh-environments, such as automotive. Our TEC solution enables the use of commodity off-the-shelf DRAMs in safety-critical applications by reducing the temperature conditions to a range where they can operate reliably. This TEC solution is applied a posteriori to the DRAM chips without using high-cost package solutions. Thus, it maintains the low-cost targets of such devices, improves the reliability, and at the same time, counterbalances the adverse effects of increasing the refresh rate. To quantitatively evaluate the benefits of TEC on commodity DRAMs in harsh-environments, we performed system-level evaluations with several applications backed up by the measured data on commodity DRAMs. Our experimental results, using accurate multi-physics simulations that employ finite element method, demonstrate that the TEC-based cooling ensures that the maximum temperature of all DRAM chips is always below 85°C despite that the original on-chip temperature (i.e., in the absence of our TEC based cooling) goes beyond 120°C.

In this work, the dynamic behavior of gallium nitride on silicon high electron mobility transistors (GaN/Si HEMT) with carbon doped buffer is modeled using a finite state machine embedded into the core Advanced SPICE Model for High Electron Mobility Transistor (ASM-HEMT). The model is based on the physics of trapping and detrapping of electrons in carbon at nitrogen-site acceptor trap (denoted here as $\text{C}_{N}$ ) and does not require an equivalent Resistance-Capacitance circuit. The model is validated against three off-state stress drain voltages of 50 V, 100 V, and 150 V using only $\text{C}_{N}$ as trap species.

The model predictive current control (MPCC) method has been widely used in permanent magnet synchronous motor (PMSM) drive systems for excellent dynamic performance. The fault diagnosis of the PMSM drive system becomes as important as dynamic performance improvement. The open-circuit fault of the semiconductor power switches is commonly seen in the PMSM drive system, which causes safety issues due to the abnormal operation of the system if the fault has not been detected. However, the previous fault diagnosis methods are mainly aimed at PMSM drive systems with conventional control methods. Focused on PMSM drive system with MPCC method, a diagnosis method of semiconductor power switch open-circuit fault has been proposed. The calculated result of the cost function in implementing the MPCC algorithm has been picked as the primary characteristic parameter for fault diagnosis, which is derived through comparative analysis of the operation in fault conditions with normal conditions. In addition, the monitored stator current and the gate-driving signals of the switches are used as subordinate fault characteristic parameters. The selected three fault indices together with a digital filtering algorithm complete the switches’ open-circuit fault diagnosis. A MATLAB/Simulink model has been built to validate the effectiveness of the proposed fault diagnosis method. The simulation results verify the proposed method’s robustness against the operating point and parameter mismatch of the PMSM drive system.

The arrival on the market of new power devices based on wide bandgap semiconductors has raised a relevant interest due to their superior properties compared to conventional technologies. On the other hand, these devices are inherently characterized by high rates of voltage changes over time, which may result in reliability challenges in electric drives adopting them. In fact, dangerous voltage overshoots at the motor terminals and uneven voltage distributions within the machine windings may occur. These phenomena can trigger a high insulation stress and partial discharges and, as a consequence, they may concur to the premature failure of the dielectric materials. This paper proposes a flexible and comprehensive modelling approach for the accurate analysis and estimation of both voltage overshoots and voltage distributions in a typical converter-cable-motor system intended for more electric aircraft applications. The modelling results are validated against experimental measurements carried out on a physical prototype comprising a wide bandgap-based converter, a connecting cable and an electrical machine stator. The findings are then used in the companion papers (part II and part III) to investigate the dependence of partial discharge phenomena on these voltage waveforms, highlight reliability challenges in modern ±270 V DC bus voltage drives for the more electric aircraft and discuss solutions.

Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced technology nodes. In this paper, we extracted the parasitic and intrinsic capacitances of a silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt to accurately compare its capacitances and, consequently, circuit-level performances to CMOS at comparable nodes. Analytical models of the parasitic capacitances of a TIGFET transistor were derived using techniques such as the equivalent Schwarz-Christoffel transformation and standard cylindrical capacitors and show close agreement with numerical simulations. The maximum capacitance of a TIGFET transistor is $2\times $ larger than for a 15 nm CMOS High Performance (HP) device due to the TIGFET’s two additional gated contacts, but this is countered by its ability for multiple modes of operation which reduces the effective switching capacitance per device. A TIGFET transistor sees, on average, only a 30% increase in total capacitance compared to a CMOS HP device. Additionally, the TIGFET’s increased device functionality can be used to modify the circuit-level architecture of a TIGFET-based design to mitigate the performance impact of its larger device-level capacitance. This combination of a TIGFET’s (1) multiple modes of operation, and (2) circuit-level architecture lead to enhanced system performance. In particular, we show that at the 15 nm technology node TIGFET technology has 18% lower energy-delay product for a fan-out of 4 and higher when using 1-bit full-adder logic circuit than for the equivalent node CMOS HP.

In this paper, a discrimination method is proposed for the interturn short-circuit and resistive unbalance faults of the synchronous condenser. The mathematical models of the synchronous condenser are established under these two faults. Especially, the zero-sequence voltage components (ZSVC) under two faults are analyzed. Due to the direct connection between the synchronous condenser and the power grid, the fundamental component of ZSVC under the interturn short-circuit fault is not affected by the stator currents, while the resistive unbalance fault is just the opposite. Hence, the amplitude of fundamental component in ZSVC is used to detect the fault occurrence. Then, the change of the fundamental component in ZSVC is observed by changing the excitation current to discriminate the fault type. The effectiveness of the proposed method is verified by the simulation and experimental results.

Nowadays, photovoltaic (PV) systems based on centralized topology with a three-level T-type (3LT2) inverter are used to decrease investment costs and increase conversion efficiency. In this topology, the split capacitors of the DC-link can individually connected to PV arrays. Accordingly, DC-link capacitors’ voltage should separately controlled to track PV arrays’ maximum power point (MPP) voltage. However, the asymmetric control of capacitors’ voltage causes line voltage to unbalance and output current to distort. In this paper, a hybrid method based on dipolar variable injection and zero-sequence voltage injection concepts is proposed to simultaneously control the DC-link capacitors’ voltage of the 3LT2 inverter and eliminate their voltages ripple. In the presence of partial shading, the proposed method can control the capacitors’ voltage of the DC-link to realize the separate MPP tracking while ensuring the balance of line voltages. Furthermore, the proposed method eliminates the voltage ripple on DC-link capacitors, inherently caused by the 3LT2 inverter, to improve the DC-link lifetime and the PV system reliability. The simulation studies and practical experiments have been performed, and their results prove the validity of the proposed method, whether the PF is unity or non-unity.

We present an X-band two-stage power amplifier (PA) in 65-nm CMOS process using a transformer (TF)-based voltage combining technique (VTC) which achieves the highest figure of merit (FOM) among recently reported CMOS PAs. The PA architecture is constructed with two-stage push-pull amplifiers with a three-way voltage power combiner and splitter which play the main role to achieve outstanding performance. The power combining was applied in the voltage domain to increase the output device size aiming at boosting the output power of the CMOS PA. We constructed a compact two-stage PA with a push-pull structure with conjugate matchings at the input, inter-stage, and output with the capacitive neutralization technique to improve the power gain and drain efficiency. Working under a 1.2-V supply with DC quiescent current of 865-mA, the proposed PA achieved a maximum saturated output power of 25.1 dBm with a 1-dB power bandwidth of 3-GHz from 8.4-GHz to 11.4-GHz, a peak power added efficiency (PAE) of 25.4% at 10.2 GHz, a power gain of 25.9-dB at 9.5-GHz with a 3-dB gain bandwidth of 2-GHz (8.7-10.7 GHz). The total chip size is 0.9 mm2, and the core size excluding pads is only 0.342 mm2.

This paper presents the concept and results of a novel resonant DC-DC converter which achieves high voltage gain at a low number of utilized switches, low voltage stress on transistors, ZVS and ZCS operation, high efficiency and variable voltage gain. The converter uses resonant switched-capacitors (SC) circuits with five switches which allows it to reach a six-fold voltage gain. By the application of adequate switching patterns, seven levels of voltage adjustment can be achieved. The basic operation mode of the converter is at zero current switching (ZCS) but a part of the existing transitions can be switched-on at a zero drain-source voltage. Zero voltage switching (ZVS) allows for a reduction of $C_{\mathrm {oss}}$ losses and a decrease in disturbances of voltages and currents. In the proposed converter, voltage stress on switches are noticeably lower than the output voltage which is beneficial from viewpoint the cost reduction and switching quality improvement. The converter output stage consists of two series connected capacitors which allows for a supply of 3-level NPC inverters. Resonant inductors, used in the proposed topology, store very low amount of energy and their volume is significantly lower than in case of chokes typically used in switch-mode converters. Qualities of the converter such as low switch count, efficiency, ZCS and ZVS operation as well as voltage gain variation are demonstrated in this paper. Furthermore, an impact of MOSFET transistors type on the efficiency of the converter is investigated. The design based on low $C_{\mathrm {oss}}$ superjunction (SJ) MOSFETs is compared with the implementation where $R_{\mathrm {ds(on)}}$ of switches is minimized. Due to low voltage stress, application of Schottky rectifiers is also demonstrated in the converter. The concept of the topology and switching patterns is verified by the results of analysis, simulations and experiments.

A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed architecture with a shared 6-bit Flash ADC and time interleaved SAR ADC provides a power and area efficient high speed ADC. The proposed Time-skew calibration is implemented to minimize the discrepancy between the output of Flash ADC and SAR ADC’s channels. To rectify the decision error of the Flash ADC and extract the time-skew information, 1-bit redundancy is included in the CDAC of the SAR conversion. The decision error between the Flash ADC and the SAR ADC is covered with designed redundancy and the mismatch between the ADCs is covered with the time-skew calibration. To reduce the offset mismatch between Flash and SAR ADC and within SAR ADCs, all comparators are calibrated to minimize their absolute offset by utilizing background offset calibration. The modified dynamic strong ARM comparator is used for flash ADC and dynamic latched comparator is used for SAR ADCs. For fine offset calibration and low power consumption, the comparator’s offset calibration circuit is implemented. To reduce the kickback noise and enhance the overall energy efficiency for fast operation of SAR ADCs, rail-to-rail dynamic latch comparator with modified adaptive power control (APC) is implemented. The proposed ADC structure has been implemented in 130 nm CMOS process. The ADC has an effective number of bit (ENOB) of 10.97 bits while consuming 7.08 mW current consumption from the 1.2 V supply voltage.

Insulator failure is one of the important causes of railway power transmission accidents. In the automatic detection system of railway insulators, the detection and classification of insulator faults is a challenging task due to the complex background, small insulators and unobvious failures. In this article, we propose a railway insulator fault detection network based on convolutional neural network, which can detect faulty insulators from images with high resolution and complex background. The insulator fault detection network realizes the position detection and fault classification of the insulator by cascading the detection network and the fault classification network. The method of cascading two networks can reduce the amount of network calculations and improve the accuracy of fault classification. The insulator detection network uses low-resolution images for position detection, and this method can prevent the detection network from paying too much attention to the details of the image, thereby reducing the amount of network calculations. The fault classification network uses high-resolution insulator images for fault classification. The high-resolution images in this method have rich detailed information, which helps to improve the accuracy of fault classification. The trained insulator detection network and the fault classification network are cascaded to form an insulator fault detection network. The precision, recall and mAP values of the insulator fault detection network are 94.10%, 92.88% and 93.46% respectively. Experiment shows show that this network cascading method can significantly improve the accuracy and robustness of insulator fault detection.

To detect the three-phase current in the complex plane of a DC link shunt inverter, an algorithm for restoring the current is required. In this paper, a method of dividing the detection voltage and the compensation voltage to match the output voltage as much as possible to reduce the total harmonic distortion while restoring the current is proposed. In addition, an overmodulation algorithm for a 12-step output, which corresponds to the largest voltage in a DC link shunt inverter, is proposed, and a current recovery method in the overmodulation region is proposed. To determine how to ensure a linear output voltage, the fundamental frequency of the output voltage is analyzed through a Fourier series, and a new voltage vector whose fundamental frequency amplitude is equal to the amplitude of the command voltage is calculated. Finally, the performance of the proposed algorithm is verified through simulation and experimentation. The output of a motor was increased by using overmodulation, and the harmonics of the current based on the output voltage were analyzed through a Fourier series.

This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integrate multiple subarrays of different dimensions to generate larger capacity SRAM arrays. The compiler is demonstrated in a commercial-grade M3D process design kit (PDK) with two tiers of carbon nanotube transistors (CNFETs). Simulations show that the M3D CNT SRAM design can improve the properties of memory compared to the 2-D CNT SRAM design. In a 32-kB memory implementation, the M3D design can reduce footprint, latency, and energy by 33%, 10%, and 19%, respectively. The compiler is used to show the feasibility of fine-grain logic and SRAM stacking in M3D technology.

This article demonstrates a digitally friendly time-based analog-to-digital converter (ADC) exploiting Dickson charge-pump (CP) as part of a voltage-to-time conversion (VTC) implemented in 28-nm CMOS. In the proposed technique, the Dickson CP generates a ramp signal that is compared with the input voltage to generate a pulse of commensurable widths, which is then fed to a D-type flip-flop (DFF)-based time-to-digital converter (TDC). The TDC is composed of CMOS DFFs and digital circuits for digital conversion without any use of analog-intensive circuits, e.g., amplifiers or current sources. Thanks to the robustness of Dickson CP characteristics, the digital outputs of the proposed ADC can be corrected through a low-complexity deterministic digital mapping with improvements of 1.5-bit in peak effective number of bits (ENOB) and 9 dB in peak signal-to-noise-and-distortion ratio (SNDR) verified over three measured sample prototypes.

Static random-access memory (SRAM) is an essential component for realizing large-scale integration (LSI). The future transition to a 48 V DC supply in datacenters and electric vehicles acting as mobile edge servers will increase the demand for a bipolar-complementary metal-oxide semiconductor-double diffused metal-oxide semiconductor with high-capacity SRAM. When we scaled and optimized an SRAM cell from 130 nm nodes to 90 nm nodes, we observed the generation of crystal defects induced by mechanical stress in the p-channel MOS active area that cannot be explained by previous models. We performed simulations using the finite element method to identify the mechanism. In our results, the edge of the narrow active area showed a large deformation compared to the middle of the active area, which can be attributed to compressive stress from the gate electrode and sidewall. The cell layout and sidewall structure were optimized to suppress this defect generation while satisfying reliability requirements, and the design can be extended to 65 nm nodes.

As the power interface between the energy storage devices (ESD) and the dc link of DC Micro-grids, dc-dc converters, which have been regarded as the heart of many critical applications such as electrical vehicles, data center, and aerospace power systems, have gained more and more attentions recently. The fault diagnosis and tolerant control in dc-dc converters become essential to ensure a reliable and robust power system especially for critical applicants, where a sudden stoppage, loss of functionality, or degradation of performance might result in a catastrophe. This paper focuses on different types of faults in dc-dc converters by analyzing main failure spots and mechanism, covering catastrophic fault and parametric fault from component to system. A comprehensive review of the up-to-date fault mode analysis, fault diagnosis signals and algorithms, and fault tolerant control in various dc-dc topologies has been presented. This research will provide a useful design guideline for the reliability improvement in all forms of dc-dc converters.

This paper presents a new voltage-mode elliptic band-pass filter based on a multiple-input transconductor (MI-OTA). The MI-OTA’s structure employs the multiple-input MOS transistor technique that simply enables to increase the number of OTA’s inputs without increasing the number of current branches or the differential pairs. The MI-OTA features high linearity over a wide input range with a compact and simple CMOS structure. From the advantage of multiple inputs, it enables to construct the arbitrarily summing and subtracting under the proposed voltage-mode filter design procedure. The filter is designed and simulated in Cadence environment using $0.18~\mu \text{m}$ TSMC CMOS technology. The filter offers 72.9 dB dynamic range for 2 % total harmonic distortion (THD) for sine input signal of 0.5 Vpp @ 1kHz with voltage supply ± 0.9V. The simulation results of the filter are in agreement with the RLC prototype. The experimental results using commercially available IC are also included to confirm the proposed filter that are in good agreement with the simulation results.