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Intel is among the most popular microprocessor architectures introduced till to date. An extensively large number of applications have been developed on Intel ISA over the last more than three decades. However, Intel architectures also suffered intentionally or unintentionally from the cyber security related issues like Spectre, Meltdown and ZombieLoad. As compared to ARM & MIPS architectures, Intel is strictly proprietary; therefore it gives only minimal provision to implement safeguards against security threats at architectural level by its large scale users. In this work, we propose a heterogeneous microprocessor architecture named as ARMINTEL derived from our base concept of ARM inside Intel. Armintel uses an Intel front-end and an ARM back-end in its microarchitecture to make user able to run the applications developed for Intel in a secure execution environment of ARM. The contributions of this work are quad-fold starting from proposal on a heterogeneous microprocessor architecture, establishing its feasibility by driving Intel ISA mappings on ARM ISA, development of a complete simulation framework for functional evaluations of Armintel and last but not least is the performance estimation by adding cycle level measurements in the simulator. The results show that this new architecture can help replace security hazardous of Intel regime to a safer option of using open source ARM cores with front-end design to accept Intel binaries.

Safe transportation of temperature sensitive medicines and vaccines require controlled temperature environment that is critical for preservation of their potency. This paper describes the design and development of automatic temperature controlled portable cooling cabinet that can be used for transportation of sensitive medicines or vaccines. A solid State device based on semiconductor junctions called peltier module is used for maintaining desired temperature. Peltier module based cooling system can be designed for any such application that require controlled temperature environment. The said module absorbs heat energy from cabinet with aid of heat exchanger and dissipates this energy on its opposite side with help of another heat exchanger. Extruded rectangular fin aluminum heat sinks were used as heat exchanger that effectively increases the surface area. Heat sinks are air cooled but to facilitate heat transfer between ambient air and heat sink, forced convection has been used. A closed loop feedback controller is also implemented to maintain the desired temperature range inside cabinet, using ON-OFF control for peltier module. Experiments were conducted for desired temperature ranges and performance of system is evaluated. To the best of their knowledge the authors feel that suggested setup is not only cost effective but also energy efficient as compared to conventional vapor compression cooling Systems.

Online Tap Changer (OLTC) are employed in transformers to regulate the bus voltage. Mechanical OLTC are being used commonly in the transformer. An introduction to the electronic online tap changer is given. A design for the winding and switch arrangement for the electronic tap changer transformer is discussed. Then using this winding structure and switch arrangement an optimal topology is presented, realization of bi-directional switch and its commutation is also presented. A model for the controller of an electronic tap changer is designed by making some modifications in conventional controller.

Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. Spatial locality of processing cores in a multi-core chip can be exploited to gain computational efficiency of a network on chip. In this paper we propose a new criterion in performance evaluation of NoC architecture that is based on the concept of group locality in an interconnection network, the "lower layer complete connect". TriBA a new idea in multi-core architectures and a direct interconnection network (DIN), is compared with 2D Mesh on single chip multi core architecture. TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized for getting maximum out of an on-chip interconnection of cores. Cores on the same chip are connected via triplet-based hierarchical interconnection network (THIN), which has simple topology and computing locality characteristic. We have modeled execution of dense matrix and sorting algorithm on an on-chip multi core interconnection network. Our results show that Triplet Based interconnection architecture has strong spatial locality characteristics in comparison to the conventional 2D mesh. The computational efficiency of Triplet based interconnection is remarkable when the number of processing cores increase substantially.

This paper presents a flexible two-layer buffer caching scheme to improve the performance of storage cache which is used to serve multiple concurrently accessing applications with diverse access patterns. To achieve this, the proposed scheme dynamically partitions the cache among applications. At the first layer, it uses a configurable global cache allocation policy to make adaptive cache allocations in response to the evolving access patterns of competing applications. In contrast to traditional global replacement approach, the allocation policy adopted in our scheme utilizes application’s marginal utility but not cache demand for allocation, so as to minimize the total number of cache misses. At the second laver, our scheme tries to maximize the utilization of allocated cache blocks by applying each application with an appropriate local replacement algorithm based on its access pattern. We have implemented our scheme in Linux kernel 2.6.18 as a pseudo device driver and measured its performance using various real-life workloads. The experiment results show that compared with Linux page cache, the proposed scheme can reduce the overall response time by up to 2 times with an average of 50% and reduce the overall disk load by up to 31% with an average of 21%.

We have entered the era of many-core processors and complex SoCs, where on-chip interconnection networks play a dominant role in determining the performance, power, and ultimately cost of a system. Therefore, interconnection strategy that supports efficient communication between IP blocks is essential. Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. We propose a new criterion in performance evaluation that is based on the concept of group locality in an interconnection network, the “lower layer complete connect”. Our proposed criterion depicts how completely a processing node is connected to all its neighbors. In this paper we evaluate TriBA, a class of direct interconnection network (DIN), for multi-core on-chip interconnection architecture. TriBA is compared with 2D Mesh as static interconnection networks for VLSI implementation. The criteria of evaluation are enumerated from two orthogonal view points, viz., computational speed and physical layout. We conclude that TriBA has the potential to have significantly better performance as an on-chip interconnection network for future MPSoC systems.

This paper evaluates the performance of triplet based architecture, TriBA - a new idea in multiprocessor architectures. TriBA is compared with two types of static interconnection networks for VLSI implementation. The interconnection networks used for comparison are well-known in literature as two-dimensional mesh and binary tree. The evaluation criteria has been selected from three orthogonal entities - physical (chip area and dissipation), computational speed (message delay) and cost (chip yield, layout cost). TriBA is a new solution for computer architecture, which is believed to be suitable for sophisticated embedded applications with multiple concurrent processing centers. TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors. TriBA is an object-oriented chip multi-processor structure that supports truly parallel execution of objects from hardware. Cores on the same chip are connected via triplet-based hierarchical interconnection network (THIN), which has simple topology and computing locality characteristic. The root of "triplet based architecture" is based on the concept that "complex problems can be decomposed to three relatively independent sub-problems, which are data processing, data management and data communication" TriBA manifests great similarity to the hierarchal structure of object systems, so that the software and computer system achieve a certain degree of structural unity.

The key to a good fuzzy control system is its fuzzy control query table, and the system's performance mainly depends on the quality of the table. Based on analyzing fully the principles of a typical fuzzy control systems and the procedures of building a fuzzy control table, this paper presents a new method of applying the Boolean association rule data mining techniques to mining of fuzzy control query table directly from the database of manual operating records.

An optimized design for capturing still images from a high altitude balloon flights has been developed. The architectural models produced are well suited for FPGA implementation, which has been the ultimate goal of the authors. The models have successfully achieved the requirements of hardware implementation, where the number of calculation, especially the multiplications, involved in transformation has been reduced significantly.

Multiuser detection is central to the fulfillment of the capabilities of code-division multiple access (CDMA), which is becoming the ubiquitous air-interface in future generation communication systems. In DS-CDMA communications, all user signals overlap in time and frequency and cause mutual interference. The conventional DS-CDMA detector follows a single-detection strategy in which each user is detected separately without regard for the other users. A better strategy is multi-user detection, where information about multiple users is to improve detection of each individual user. Multi-user detection (MUD) is the intelligent estimation/demodulation of transmitted bits in presence of multiple access interference (MAI). Unlike additive white Gaussian noise (AWGN), MAI has a nice correlative structure that is quantified by the correlation matrix of the signature sequences. This paper describes and analyses linear multi-user DS-CDMA detectors. The most popular detectors include the decorrelating detector and MMSE detector.