116 results on '"Heyns M"'
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2. Magnetic domain walls: from physics to devices
3. Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process
4. 50 nm Gate Length FinFET Biosensor & the Outlook for Single-Molecule Detection
5. All-electrical control of scaled spin logic devices based on domain wall motion
6. BioFET Technology: Aggressively Scaled pMOS FinFET as Biosensor
7. HfZrO Ferroelectric Characterization and Parameterization of Response to Arbitrary Excitation Waveform
8. Scaled spintronic logic device based on domain wall motion in magnetically interconnected tunnel junctions
9. Investigation of ferroelectric HfZrO FET for steep slope applications
10. Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs
11. Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited)
12. First demonstration of ∼3500 cm2/V-s electron mobility and sufficient BTI reliability (max Vov up to 0.6V) In0.53Ga0.47As nFET using an IL/LaSiOx/HfO2 gate stack
13. Transistors on two-dimensional semiconductors: contact resistance limited by the contact edges
14. Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole
15. Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation
16. Novel method to determine the band offset in hetero staggered bandgap TFET using Esaki diodes
17. The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices
18. BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities
19. BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs
20. Band-to-band tunneling in MOS-capacitors for rapid tunnel-FET characterization
21. Suitability of high-k gate oxides for III–V devices: A PBTI study in In0.53Ga0.47As devices with Al2O3
22. An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates
23. Towards the Monolithic Integration of III-V Compound Semiconductors on Si: Selective Area Growth in High Aspect Ratio Structures vs. Strain Relaxed Buffer-Mediated Epitaxy
24. Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications
25. Challenges for introducing Ge and III/V devices into CMOS technologies
26. Advancing CMOS beyond the Si roadmap with Ge and III/V devices
27. Novel architecture to boost the vertical tunneling in Tunnel Field Effect Transistors
28. Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions
29. Great reduction of interfacial traps in Al2O3/GaAs (100) starting with Ga-rich surface and through systematic thermal annealing
30. Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution
31. Germanium for advanced CMOS anno 2009: a SWOT analysis
32. Fundamentals and extraction of velocity saturation in sub-100nm (110)-Si and (100)-Ge
33. Advanced electrical characterization toward (sub) 1nm EOT HfSiON ¿ hole trapping in PFET and L-dependent effects
34. High Performance High-k/Metal Gate Ge pMOSFETs with gate lengths down to 125 nm and halo implant
35. Analysis of junction leakage in advanced germanium P+/n junctions
36. High performance Ge pMOS devices using a Si-compatible process flow
37. Cross-wafer controlled interface layer thickness variation, and its application to SiO2 / high-¿ stack characterisation
38. Roadblocks and Critical Aspects of Cleaning for Sub-65nm Technologies
39. Impact of Nitrogen Incorporation in SiOx/HfSiO Gate Stacks on Negative Bias Temperature Instabilities
40. On the Recovery of Simulated Plasma Process Induced Damage in High-κ Dielectrics
41. On the Recovery of Simulated Plasma Process Induced Damage in High-κ Dielectrics
42. Ge Deep Sub-Micron HiK/MG pFET with Superior Drive Compared to Si HiK/MG State-of-the-Art Reference
43. Effects of interactions between HfO2 and poly-Si on MOSCAP and MOSFET electrical behavior
44. Implementation of high-k gate dielectrics - a status update
45. Ge and III/V devices for advanced CMOS.
46. On the Recovery of Simulated Plasma Process Induced Damage in High-κ Dielectrics.
47. Cross-wafer controlled interface layer thickness variation, and its application to SiO2 / high-κ stack characterisation.
48. A new method to calculate leakage current and its applications for sub-45nm MOSFETs.
49. Achievements and challenges for the electrical performance of MOSFETs with high-k gate dielectrics.
50. Interface passivation mechanisms in metal gated oxide capacitors.
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