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Your search keyword '"Hiroaki Iwaki"' showing total 4 results
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4 results on '"Hiroaki Iwaki"'

1. A mixed asymmetric/symmetric (MASS) MOSFET cell for ASICs

Author

K. Nakajima, Hiroaki Iwaki, A. Asahina, Akira Yoshino, Susumu Kurosawa, N. Hamatake, K. Ohuchi, Koichiro Okumura, Y. Yamazaki, and Kouichi Kumagai

Subjects
Engineering, business.industry, Hardware_PERFORMANCEANDRELIABILITY, Integrated circuit layout, CMOS, Application-specific integrated circuit, MOSFET, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Cmos logic circuits, Optoelectronics, business, Hardware_LOGICDESIGN, Block (data storage)
Abstract

A new basic cell for ASICs which embeds fixed asymmetric and symmetric (MASS) LDD MOSFETs is proposed. A 142 KG MASS cell SOG has been developed using a half micron CMOS technology with two extra masks. The MASS cell has no area penalty for static latch and flip-flop block layout, and it has 13% drivability improvement without high cost and fine process technology. The advantages of the MASS cell application to ASICs have been confirmed. >

Published
2002

2. A 3D analysis of source/drain capacitance in SOI MOSFET for practical circuit design

Author

Akira Yoshino, Susumu Kurosawa, Kouichi Kumagai, and Hiroaki Iwaki

Subjects
Coupling, Engineering, Differential capacitance, business.industry, Circuit design, Transistor, Electrical engineering, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, Capacitance, law.invention, Parasitic capacitance, law, MOSFET, Hardware_INTEGRATEDCIRCUITS, business, Hardware_LOGICDESIGN
Abstract

It is well known that the small capacitance of the source/drain (S/D) region in MOS/SOI devices is one of the most attractive characteristics for the circuit performance improvements. In order to perform the implementation of the three-dimensional (3D) effects of the S/D capacitance into circuit simulators for more precise simulations, it is strongly required to estimate 3D dependence of the S/D capacitance on transistor layout patterns. However, such effects of the 3D coupling between the adjacent S/D regions have not been investigated in detail. In this study, we analyzed 3D effects of the S/D capacitance in MOS/SOI devices using in-house simulators, and discussed the contribution of the 3D effects on the total S/D capacitance.

Published
2002

3. A novel powering-down scheme for low Vt CMOS circuits

Author

Kouichi Kumagai, H. Yoshida, Hiroaki Iwaki, S. Kurosawa, H. Suzuki, and T. Yamada

Subjects
Adiabatic circuit, Engineering, business.industry, Electrical engineering, Mixed-signal integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, Integrated circuit design, Integrated injection logic, CMOS, Low-power electronics, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, IC power-supply pin, business, Hardware_LOGICDESIGN, Electronic circuit
Abstract

In this paper, a novel powering-down scheme with a virtual power/ground rails clamp (VRC) circuit is proposed. It features the 98% off-leakage current reduction, without the operating speed degradation and the high Vt transistors. The VRC scheme does not need the extra circuits and the timing design for data holding in the sleep mode. This effectiveness has been confirmed by the 24-bit multiplier-accumulator, using 0.25 /spl mu/m CMOS double-layer metal technology.

Published
2002

4. A new SRAM cell design using 0.35 μm CMOS/SIMOX technology

Author

Hiroaki Iwaki, Susumu Kurosawa, K. Imai, H. Onishi, Y. Matsubara, T. Yamada, H. Nakamura, and Kouichi Kumagai

Subjects
Hardware_MEMORYSTRUCTURES, Materials science, business.industry, Sram cell, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, Integrated circuit design, CMOS, Memory cell, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Optoelectronics, Equivalent circuit, Static random-access memory, Macro, business, Hardware_LOGICDESIGN
Abstract

In SOI/CMOS devices, it is known that the integration density and the circuit performance can be improved using a layout of abutted n/sup +/ and p/sup +/ drain regions. Utilizing these advantages in the SOI technology, we have designed a new 6-T memory cell and have developed a 128 Kb synchronous SRAM macro (SOI-SRAM) by 0.35 /spl mu/m CMOS/SIMOX technology. The SOI-SRAM performance is compared with the reference SRAM macro (REF-SRAM) which is designed with the bulk CMOS memory cell layout.

Published
2002

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