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Nexans experience in developing all CSD processes for coated conductors with the YBCO/CGO/LZO/Ni–5% W RABITS architecture is summarized. The chosen CC architecture has a principal disadvantage that the next layer only clones, but more often deteriorates the out-of-plane texture of the previous layer (in average by \sim20% for LZO). Depending on the quality of RABITS, this may increase the amount of grain boundaries (GBs) not transparent for the supercurrent close to the percolation limit for the current-breaking path, which explains low and poorly reproducible Jc. Modifying the buffer architecture by introducing CGO seed layer suppresses deterioration of the out-of-plane texture. Another approach, extending the range of acceptable grain misorientations by selective doping YBCO GBs with Ca is shown not possible using the current MOD-TFA process because of decomposition of initial Y123 to disordered Y124 and Y247 during pyrolysis of the second MOD layer. Possible ways of further development are discussed. [ABSTRACT FROM AUTHOR]