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This paper overviews the motion vector coding and block merging techniques in the Versatile Video Coding (VVC) standard developed by the Joint Video Experts Team (JVET). In general, inter-prediction techniques in VVC can be classified into two major groups: “whole block-based inter prediction” and “subblock-based inter prediction”. In this paper, we focus on techniques for whole block-based inter prediction. As in its predecessor, High Efficiency Video Coding (HEVC), whole block-based inter prediction in VVC is represented by adaptive motion vector prediction (AMVP) mode or merge mode. Newly introduced features purely for AMVP mode include symmetric motion vector difference and adaptive motion vector resolution. The features purely for merge mode include pairwise average merge, merge with motion vector difference, combined inter-intra prediction and geometric partitioning mode. Coding tools such as history-based motion vector prediction and bidirectional prediction with coding unit weights can be applied on both AMVP mode and merge mode. This paper discusses the design principles and the implementation of the new inter-prediction methods. Using objective metrics, simulation results show that the methods overviewed in the paper can jointly achieve 6.2% and 4.7% BD-rate savings on average with the random access and low-delay configurations, respectively. Significant subjective picture quality improvements of some tools are also reported when comparing the resulting pictures at same bitrates. [ABSTRACT FROM AUTHOR]

This paper describes a video coding technology proposal submitted by MediaTek in April 2018 in response to a joint call for proposals (CfP) issued by ITU-T VCEG and ISO/IEC MPEG. The proposal uses the conventional block-based hybrid coding approach with a breakthrough design of block structure, substantial improvements of coding tools, and new inventions of loop filtering techniques. First, the block structure is designed using a highly flexible partitioning scheme, where each coding tree unit in a picture is split into multiple coding units (CUs) by a recursive quaternary tree followed by a recursive binary-ternary tree. The prediction unit (PU) and transform unit (TU) concepts are unified with the CU concept, i.e., PU and TU are basically the same as CU. Moreover, inter prediction, intra prediction, transform, quantization, in-loop filtering, and entropy coding are all improved. Finally, new loop filtering techniques are invented, where the proposed convolutional neural network loop filtering is of particular interest. The proposed video codec achieves 43.81% average bit rate savings based on objective measures compared to the High Efficiency Video Coding (HEVC) anchors and is among the best-performing CfP responses both objectively and subjectively. It has been partially adopted into the working draft of the Versatile Video Coding (VVC) standard. [ABSTRACT FROM AUTHOR]

This paper concentrates on the computationally efficient sub-connected mapping strategies from radio frequency (RF) chains to antennas in millimeter wave (mmWave) massive multiple input multiple output (MIMO) systems with hybrid RF/baseband precoding/combining design. Such an adaptive subarray architecture offers a tradeoff between hardware complexity and spectral efficiency in massive MIMO networks at mmWave frequencies. Three proposed low-complexity dynamically connected structures comprise the Manhattan metric (MM) with/without overlapping, contiguous subarray correlation (CSC), and equally neighboring correlation design techniques. On the basis of the achievable sum-rate (ASR) maximization, the proposed adaptive RF chain-antenna planning methodologies are used to reconfigure effectively RF-chain associated subarrays. Remarkably, both the nonoverlapped MM and the CSC dynamically connected configurations possess excellent advantages of ASR performance and computational complexity simultaneously at a fixed hardware requirement in terms of phase shifters. Finally, simulation results demonstrate that the proposed adaptive partially connected networks are capable of accomplishing an ASR capacity approaching the fully digital and fully connected design with an alleviated demand on both computation and hardware complexities. Furthermore, with the same amount of phase shifters, all the proposed dynamically constructed subarrays outperform the partially connected but fixed architectures. [ABSTRACT FROM AUTHOR]

Resonant frequency of an LCL filter in a grid-connected inverter is an important factor for control stability and grid-injected current quality. However, the constraints on resonant frequency are usually considered as an afterthought in conventional filter design methods. The fact that resonant frequency is affected by both internal and external factors during operation makes it even more critical. Hence, an improved resonant frequency based systematic LCL filter design method is presented in this paper. A resonant frequency band is identified by considering grid-voltage harmonics and control stability boundary. The variation in resonant frequency due to inductive line impedance as well as magnetic permeability of inductor core is taken into account to define the constraints on LCL parameters. The LCL parameters are then systematically derived from the identified constraints with almost no iteration. A division–summation (D-Σ) digital control method is used to validate the design method. Experimental results measured from a 5-kW single-phase grid-connected inverter have verified the effectiveness of the LCL filter design method over conventional methods. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of backgate biasing ( VBS ) on the drain current ( ID ) of ultrathin-body III-V heterojunction tunnel FET (HTFET). Compared with homojunction TFET and III-V/Ge MOSFET, this paper indicates that HTFET exhibits significantly higher I\mathrm{{\scriptstyle OFF}} ( ID at VGS = 0 V and VDS=0.5 V) modulation efficiency and the influence of VBS rapidly decreases with increasing VGS . In addition, it is observed that the change of source available states with VBS determines the ID modulation efficiency of p-type HTFET (pHTFET). Depending on the source doping concentration and operating VGS , the ID of HTFET under forward VBS can be anomalously smaller than that at VBS=0 V. Furthermore, the impacts of source/drain doping concentrations and junction properties are discussed and shown to be critical in determining the ID modulation efficiency of HTFET. We find that, under controlled ambipolar current, reverse backgate biasing can be utilized to suppress the I\mathrm{{\scriptstyle OFF}} of HTFET, and the modulation efficiency increases with decreasing source doping concentration. Our study may provide insights for device/circuit designs with advanced TFET technologies. [ABSTRACT FROM PUBLISHER]

This paper provides a technical overview of a newly added in-loop filtering technique, sample adaptive offset (SAO), in High Efficiency Video Coding (HEVC). The key idea of SAO is to reduce sample distortion by first classifying reconstructed samples into different categories, obtaining an offset for each category, and then adding the offset to each sample of the category. The offset of each category is properly calculated at the encoder and explicitly signaled to the decoder for reducing sample distortion effectively, while the classification of each sample is performed at both the encoder and the decoder for saving side information significantly. To achieve low latency of only one coding tree unit (CTU), a CTU-based syntax design is specified to adapt SAO parameters for each CTU. A CTU-based optimization algorithm can be used to derive SAO parameters of each CTU, and the SAO parameters of the CTU are inter leaved into the slice data. It is reported that SAO achieves on average 3.5% BD-rate reduction and up to 23.5% BD-rate reduction with less than 1% encoding time increase and about 2.5% decoding time increase under common test conditions of HEVC reference software version 8.0. [ABSTRACT FROM PUBLISHER]

Discusses the convergence of decomposition methods for support vector machines. Description on the general algorithm; Analysis on the convergence proof; Conclusion.