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HfO2 based ferroelectric field-effect transistors (FeFETs) are promising for low-power and high-speed non-volatile memories. However, FeFETs can be susceptible to write disturbs due to their accumulative switching behavior, which limits their application in large scale memory arrays. Here we show that FeFETs with a thin HfO2 based ferroelectric and SiNx interfacial layer are immune to pulsed write disturbs under both ${V}_{\textit {dd}}$ /2 and ${V}_{\textit {dd}}$ /3 inhibit schemes, but not to continuous write disturb. This contrasts with previous reports which found no difference between pulsed and continuous write disturbs. Our findings suggest that accumulative polarization switching is not an intrinsic property of HfO2 based FeFETs, but might be related to charge trapping dynamics instead. [ABSTRACT FROM AUTHOR]

The ferroelectric field-effect transistor (FEFET) is an emerging nonvolatile memory technology that can offer ultra-scalability, fast operation, and reduced power consumption. However, a limited understanding of FEFET physics poses challenges for optimum device design. In this article, we provide physical insights into the operation of FinFET-based FEFETs (FEFinFETs) using a phase-field framework built on time-dependent Landau–Ginzburg (TDGL) thermodynamic theory. We exploit the source–drain fringing field to stabilize a monodomain configuration in the OFF state of short channel FEFinFETs. Based on recent experiments, we first analyze the switching dynamics of FEFinFETs with low remnant polarization (${P}_{r}$) and high coercive field (${E}_{c}$) hafnium zirconium oxide (HZO) FE. We find that the switching in these FEFinFETs occurs via domain nucleation and growth from the gate metal edges at the source–drain spacers. We also show that a non-zero drain bias can be used for dynamically modulating the memory window (MW) of FEFinFET to lower its power consumption. Furthermore, we find the spacer permittivity to be a crucial design parameter to control the MW and show that a lower spacer permittivity can significantly increase the MW. Finally, we show that the commonly held idea that a large ${P}_{r}$ leads to a large MW is not always valid. For a large ${P}_{r}$ , the formation of multiple domains in the FE layer can lead to a significant reduction in the MW. In addition, these devices can suffer from low write endurance due to exposure of the interfacial oxide layer to high electric fields. [ABSTRACT FROM AUTHOR]

In this brief, we present a compact model of nanoscale ferroelectric (FE) capacitors. We first use the phase-field simulation to study the polarization switching of very small FE capacitor that contains only a few grains. We show that at higher applied voltage, the entire grain undergoes a single-domain-like switching, but at lower applied voltage, the domain wall growth mechanism dominates due to the difference between the domain wall energies of bulk and defect nuclei. To create a compact model that includes this voltage dependence, we use a time-dependent domain switching model for each discrete grain with empirical modifications capturing the two different switching mechanisms. In addition, a voltage-dependent dielectric model is included to represent the nonlinear capacitance of the FE capacitor. We verify this compact model by fitting the results of phase-field modeling results with excellent agreement. [ABSTRACT FROM AUTHOR]

A new deep learning (DL)-based parameter extraction method is presented in this brief; 50k training cases are generated by Monte Carlo simulations of these preselected parameters in Berkeley short-channel IGFET model (BSIM)-common multigate (CMG). DL models are trained using backward propagation with ${C} _{\text {gg}} - {V} _{g}$ and ${I} _{d} - {V} _{g}$ as the input and selected BSIM-CMG parameters as the output. A TCAD simulated FinFET device, calibrated to Intel 10-nm node, is used to test the DL models. The DL-based parameters extraction results show an excellent fit to capacitance and drain current data, with 0.16% rms error in ${C} _{\text {gg}} - {V} _{g}$ and 6.1% rms error in ${I} _{d} - {V} _{g}$ (0.69% rms error in above-threshold-voltage ${I} _{d} - {V} _{g}$), respectively. In addition, devices with a 10% variation in gate length and oxide thickness are successfully modeled with the trained DL model. The results show tremendous promise in using the DL-based models for parameter extraction. [ABSTRACT FROM AUTHOR]

In this letter, we present a compact model of ferroelectric field-effect-transistor (FEFET). The model consists of a ferroelectric (FE) capacitor model and a Berkeley Short-channel IGFET Model (BSIM), a standard SPICE MOSFET model. The FE model, similar to the nucleation-limited-switching model, is based on the statistical multidomain dynamics of FE materials. The charge equality between FE and MOSFET is satisfied through the SPICE simulator. The model reproduces the steep switching in the reverse bias region observed in experimental FEFETs and the current drop at both major loop and minor loop switching. A versatile inverted-memory-window (IMW) model can model the IMW behavior of FEFET that may be caused by charge trapping. We demonstrate that the reported model can accurately fit the published data of Fin-FEFET and FDSOI-FEFET under different bias conditions. [ABSTRACT FROM AUTHOR]

In this work, we propose using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET current-voltage model. The benefits of having some physics-driven features in the model are discussed. Using a portion of the Berkeley Short-channel IGFET Common-Multi-Gate (BSIM-CMG), the industry-standard FinFET and GAAFET compact model, as the physics model and a 3-layer neural network with 6 neurons per layer, the resultant model can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3%, 4.1%, and 2.9%, respectively. Implications for circuit simulation are also discussed. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (FeFETs) based on HfO2 are promising for low-power and high-speed non-volatile memory devices. However, most reported FeFETs show limited write endurance and significant read-after-write delay due to parasitic charge trapping. Here we show that n-type FeFETs with SiNx interfacial layer and high write endurance also exhibit immediate read-after-write behavior due to negligible charge trapping. This overcomes one of the major challenges faced by FeFET technologies today. [ABSTRACT FROM AUTHOR]

In this article, we present a compact model of metal–ferroelectric (FE)–insulator–semiconductor (MFIS) tunnel junction. Unlike the metal–FE–metal (MFM) structure with only one insulator layer, MFIS–FE tunnel junction (FTJ) contains two insulator layers and a semiconductor electrode. The complex structure makes it difficult to self-consistently solve the Poisson and charge equations. We report the first compact model of MFIS-FTJ to our knowledge. Previous modeling studies focused on numerical simulation, which is time-consuming and not applicable to circuit simulation. The presented compact model is suitable for commercial SPICE IC simulation. It includes a FE model that can capture polarization switching under arbitrary applied voltage, an insulator–semiconductor model that calculates the potential profile of the MFIS stack, and an analytical tunneling current model. We demonstrate that this model can be used to simulate and fit both n-type and p-type MFIS-FTJs. [ABSTRACT FROM AUTHOR]

A single-crystal islands (SCI) technique using low thermal budget pulse laser process is proposed and demonstrated to fabricate single-crystal silicon islands over amorphous dielectric for monolithic 3-D and back-end-of-line (BEOL) FinFET circuits. By laser recrystallizing mask-defined a-Si islands encapsulated with conformal silicon nitride film, designed single-crystal Si islands can be obtained. The single crystallinity of the island are verified with SECCO Etch, high-resolution electron microscopy (HREM), transmission electron microscopy (TEM), and electron backside scattering (EBSD). About 40 nm FinFETs were successfully fabricated in the SCI Si islands and shown to exhibit excellent electrical performance and low variability that are compatible with the FinFETs fabricated on commercial silicon-on-insulator (SOI) wafer. [ABSTRACT FROM AUTHOR]

We present a compact model of polycrystalline ferroelectric (FE) capacitors. The polycrystalline thin-film material is modeled as a collection of independent grains or grain groups. Each grain or grain group is characterized by its local field-dependent switching rate, which is characterized by a distribution function such as Gaussian or type-2 generalized beta distribution. This computationally efficient model accurately reproduces the published experimental polarization switching waveforms and the switching current waveforms in response to all reported applied voltage waveforms. The model tracks the polarization history so that it can simulate the transition between major and minor and among minor loops as well as accumulative polarization which cannot be captured by the conventional models. This model is intended for simulating circuits containing FE capacitors using commercial SPICE simulators for arbitrary applied voltage waveforms. It also has the capability of simulating the discrete switching and device variability in small-area FE capacitors having a small number of grains, although there is no available experimental data to check the model accuracy in this regard. [ABSTRACT FROM AUTHOR]

This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current ($I_{\text {ON}}$). The capacitance matching and ON-state performance are evaluated using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current ($I_{\text {OFF}}$) and $I_{\text {ON}}$ relative to International Roadmap for Devices and Systems (IRDS) projections. There is a significant long-term advantage to integrated circuit (IC) power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing. [ABSTRACT FROM AUTHOR]

We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed ${I}_{D}$ dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers. [ABSTRACT FROM AUTHOR]

We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 1010 cycles. The ferroelectric transistors (FeFETs) incorporate a high- $\kappa $ interfacial layer (IL) of thermally grown silicon nitride (SiNx) and a thin 4.5 nm layer of Zr-doped FE-HfO2 (HZO) on a ~30 nm silicon on insulator (SOI) channel. The device shows a ~1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of $\text {V}_{\text {G}}= \pm \,\,3\text{V}$ at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability. [ABSTRACT FROM AUTHOR]

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and 2 μm, in an inverter circuit. At 2-μm gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors. [ABSTRACT FROM AUTHOR]

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap. [ABSTRACT FROM AUTHOR]

Gate-All-Around Field Effect Transistors (GAAFETs) for the future technology nodes will have highly confined channel cross-sections. Effects like subband separation and geometry dependent density of states result in kinks, peaks and valleys appearing in terminal characteristics like capacitance and transconductance. This has significant effect on the circuit linearity performance, in analog and RF domains. In this paper, we have proposed a design rule for the maximum allowed overdrive voltages or minimum silicon body width for a given body thickness so that the effects of subband separation may be avoided. Effect of corner radius has also been included. [ABSTRACT FROM AUTHOR]

In this paper, we develop a compact model of antiferroelectric (AFE) capacitors. AFE material, similar to the ferroelectric (FE) material, is a good candidate for non-volatile memory applications. Unlike FE materials, there are no good compact models that can describe the AFE materials for circuit simulation. In this study, we consider the AFE material as a collection of multiple crystal groups. For each group, the polarization may switch from zero to positive or negative polarization and vice versa depending on the electric field polarity. This switching is modeled by a local field-dependent switching rate, which has a statistical distribution among the groups. We implement this model in Verilog-A and run it on a commercial SPICE simulator to demonstrate this model’s capability to reproduce the published experimental data of the dependency of the AFE capacitor switching on the writing pulse width and voltage and the major and minor loops behavior are demonstrated. [ABSTRACT FROM AUTHOR]

Drain-extended MOSFET (DEMOS) with halo implant induced laterally asymmetric channel doping shows anomalous characteristics across bias and temperature that cannot be captured by existing models. The transconductance (gm) maxima in the linear region is found to be not only a function of the peak mobility but also the halo doping density. In the saturation region, the gm characteristics show a nonmonotonic “hump” induced by the halo-region/channel-region junction barrier. Another key care-about for analog design - the drain current (ID) mismatch, also exhibits unique characteristics with excess mismatch in the weak-inversion (WI) region, in particular at low temperature. In addition, the anomalous flicker noise (1/ƒ noise) trends in the presence of high-trap density in the halo region of halo-implanted DEMOS are also discussed. In this work, we propose an analytical model based on the equivalent conductance and impedance field theory to capture these effects. The proposed model is in good agreement with measurements and numerical device simulations using technology computer-aided design (TCAD) of DEMOS across a different oxide thickness, geometry, bias, and temperature. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO2(HZO) as gate insulator. ${\Omega }$ -gate transistors with gate length ~30 nm and width ~85 nm were fabricated on ~20 nm thick SOI. We demonstrate robust memory operation with ≤100 ns program and erase speed at ±5 V, projected memory retention time up to 10 years at 85 °C, and ~0.5 V memory window after 108 endurance cycles. The impact of ${V} _{\text {D}}$ on erase speed provides insights into the importance of holes on memory operation. [ABSTRACT FROM AUTHOR]

Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency (Ft) by ~10% and minimum number of substacks and minimum substack spacing should be used. [ABSTRACT FROM AUTHOR]

In this article, we will analyze and provide new insights into the polarization gradient effect of a ferroelectric using TCAD simulation and demonstrate how to model the polarization gradient effect using the negative capacitance FET (NCFET) compact model based on the BSIM framework. A larger value of g (the coefficient of polarization gradient effect) results in improved subthreshold slope, smaller OFF-current, smaller drain-induced barrier lowering (DIBL), and smaller output conductance. Inclusion of the polarization gradient effect in the NCFET compact model improves usability because it accurately captures the effects of negative DIBL and negative output conductance. [ABSTRACT FROM AUTHOR]

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously. [ABSTRACT FROM AUTHOR]

This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density (Dit) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO. [ABSTRACT FROM AUTHOR]

We propose an updated compact model for mobility in Nanosheet FETs. This is necessary since Nanosheet FETs exhibit significant mobility degradation with thickness and width scaling caused by centroid shift, changing effective mass due to quantum confinement as well as various crystal orientations of the various conduction planes. The model takes all of these effects into account. It has been implemented in Verilog-A and validated with experimental data. To the best of our knowledge, this is the first compact model capturing the effect of nanosheet scaling on mobility. [ABSTRACT FROM AUTHOR]