318 results on '"Hu, Chenming"'
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2. Compact Modeling and Experimental Validation of Reverse Mode Impact Ionization in LDMOS Transistors within the BSIM-BULK Framework
3. I-V Global Parameter Extraction for Industry Standard FinFET Compact Model using Deep Learning
4. An Improved Robust Infinitely Differentiable Drift Resistance Model for BSIM High Voltage Compact Model
5. Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs
6. Recent Enhancements in the Standard BSIM-BULK MOSFET Model
7. Optimization of Deep Learning-Based BSIM-CMG I-V Parameter Extraction in Seconds
8. Compact Model for Trap Assisted Tunneling based GIDL
9. Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs
10. On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs
11. Write Disturb-Free Ferroelectric FETs With Non-Accumulative Switching Dynamics.
12. Ge Single-Crystal-Island (Ge-SCI) Technique and BEOL Ge FinFET Switch Arrays on Top of Si Circuits for Monolithic 3D Voltage Regulators
13. Critical Importance of Nonuniform Polarization and Fringe Field Effects for Scaled Ferroelectric FinFET Memory.
14. A Compact Model of Nanoscale Ferroelectric Capacitor.
15. Deep Learning-Based BSIM-CMG Parameter Extraction for 10-nm FinFET.
16. A Compact Model of Ferroelectric Field-Effect Transistor.
17. Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling.
18. Fast Read-After-Write and Depolarization Fields in High Endurance n-Type Ferroelectric FETs.
19. First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro
20. Crystal-Orientation-Tolerant Voltage Regulator using Monolithic 3D BEOL FinFETs in Single-Crystal Islands for On-Chip Power Delivery Network
21. A Compact Model of Metal–Ferroelectric-Insulator–Semiconductor Tunnel Junction.
22. Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET
23. Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs
24. Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators
25. Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs
26. Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET
27. Physical Analysis of Non-monotonic DIBL Dependence on Back Gate Bias in Thick Front Gate Oxide FDSOI MOSFETs
28. Transient Thermal Damage Simulation for Novel Location-Controlled Grain Technique in Monolithic 3D IC
29. Single-Crystal Islands (SCI) for Monolithic 3-D and Back-End-of-Line FinFET Circuits.
30. A Compact Model of Polycrystalline Ferroelectric Capacitor.
31. S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET.
32. Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures.
33. Ferroelectric HfO2 Memory Transistors With High-κ Interfacial Layer and Write Endurance Exceeding 1010 Cycles.
34. Energy Storage and Reuse in Negative Capacitance.
35. Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET.
36. BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design
37. Ferroelectric Si-doped HfO2 Capacitors for Next-Generation Memories
38. Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits
39. Effect of Polycrystallinity and Presence of Dielectric Phases on NC-FinFET Variability
40. Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft
41. Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
42. Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity.
43. A Compact Model of Antiferroelectric Capacitor.
44. Modeling of Current Mismatch and 1/ƒ Noise for Halo-Implanted Drain-Extended MOSFETs.
45. Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors.
46. Design Optimization Techniques in Nanosheet Transistor for RF Applications.
47. Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET.
48. A Density Metric for Semiconductor Technology [Point of View].
49. Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing.
50. Compact Model for Geometry Dependent Mobility in Nanosheet FETs.
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