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Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

In this work, we perform the sensitivity analysis of negative-capacitance (NC) junctionless (JL) transistors considering the variation in device parameters and compared its performance with conventional JL devices. The OFF-current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) of the JL transistor degrades significantly as the film thickness (${T}_{{\text {si}}}$), channel doping (${N}_{\text {ch}}$), and oxide thickness (${T}_{\text {ox}}$) increase and the gate length (${L}_{g}$) decreases. However, compared to JL devices, ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ degradation due to increasing ${T}_{\text {si}}$ and ${N}_{\text {ch}}$ and decreasing ${L}_{g}$ can be effectively mitigated in NCJL devices. The reduced ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ and lower $I_{ \mathrm{\scriptscriptstyle OFF}}$ sensitivities in the NCJL transistor are due to the occurrence of more negative internal gate voltage at higher ${T}_{{\text {si}}}$ and ${N}_{{\text {ch}}}$ and lower ${L}_{g}$ , which enhances the channel depletion and reduces the ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ sensitivity. The impact of ${T}_{{\text {ox}}}$ and the spacer permittivity ($\varepsilon _{s}$) shows that reducing ${T}_{\text {ox}}$ and increasing $\varepsilon _{s}$ significantly improve the ON-current in NCJL devices due to better capacitance matching at the ON-state. Besides, for the first time, a design methodology is proposed to optimize the NCJL device for high-performance (HP) applications at ${L}_{g} = {15}$ nm. The results presented in this article serve as a guideline to extend the usability of NCJL devices for HP applications. [ABSTRACT FROM AUTHOR]

In this article, we propose an energy-efficient monolithic 3-D (M3D) three-tier SRAM cell with back-end-of-the-line (BEOL) back-gated (BG) MoS2 FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS2 FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-tier BG SRAM cell design, the proposed monolithic three-tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy- and area-efficient three-tier BG SRAM cell enables intelligent functionalities for the area- and energy-constrained edge computing devices. [ABSTRACT FROM AUTHOR]

This work demonstrates the systematic methodology to optimize the negative capacitance (NC) $n$ -type double gate (DG) junctionless (JL) device for low power (LP) and high-density (HD) applications. Results show that the positive charge density in the channel region of NCJL device induces negative internal gate voltage ($V_{\text {int}}$) at zero gate bias ($V_{\text {gs}} =0$ V), which helps to deplete the channel and significantly reduces the off-current ($I_{\text {off}}$) compared to JL device. Conventional JL device requires a very high gate work function ($\varphi _{\text {m}} \sim 5$ eV) to achieve volume depletion. However, NCJL device can lower $\varphi _{\text {m}}$ to mid-gap values while ensuring the full depletion in the channel and improving the on-current ($I_{\text {on}}$). NCJL device with mid-gap $\varphi _{\text {m}}$ exhibits higher $I_{\text {on}}$ and lower $I_{\text {off}}$ compared to the performance target specified by International Roadmap for Devices and Systems (IRDS) for LP and HD applications. [ABSTRACT FROM AUTHOR]

For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is more suitable for relaxed channel length and high-performance SRAM applications. [ABSTRACT FROM AUTHOR]