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Owing to global competition, integrated circuit (IC) design houses are facing challenges in the optimal use of capacity and resources to fulfill customer demands and maximize profit. A hybrid make-to-stock (MTS) and make-to-order (MTO) model is generally used. Wafer procurement is made according to customers’ long-term demand forecast based on MTS. Limited wafer fab resources and back-end capacity are first allocated to on-hand orders and then to forecast demand. In production planning, several factors need to be considered to determine the production quantity and inventory level, such as the material, capacity, substitute, technical constraint, and order tardiness. This study considers a typical multi-stage supply chain network of semiconductor back-end production with turnkey service for IC design houses. The objective is to maximize the total profit with the constraints of equipment capacity, the flexibility of substitutes, and the usage of the turnkey mode. The problem is formulated with a mixed-integer programming model and solved using two novel heuristic algorithms: a product-based decomposition (PD_SCP) with profit-based criteria and a Lagrangian decomposition combined with the product-based decomposition (LD-SCP) method. Using the LD-SCP algorithm takes a long time but results in a great solution. Sensitivity analysis is conducted to investigate the impact of different parameters on production cost and total profit. [ABSTRACT FROM AUTHOR]

As a transmitter power amplifier (PA), the electrical output characteristics of gallium nitride (GaN) high electron mobility transistors (HEMTs) are closely related to the drain current versus drain voltage (${I}_{d}$ – ${V}_{d}$) characteristics. Any abnormalities in the ${I}_{d}$ – ${V}_{d}$ characteristics will seriously affect device performance. Therefore, many groups have investigated the kink effect of GaN HEMTs. One of the commonly used measurement methods of the kink effect is the ${I}_{d}$ – ${V}_{d}$ forward and reverse sweep. In this study, we used the same method for Al2O3/Si3N4–AlGaN/GaN metal–insulator–semiconductor HEMT (MIS HEMT) devices. We found that not only did the kink effect occurred but ${I}_{d}$ also increased abnormally during the reverse sweep and after a series of electrical measurements. At the end of the forward sweep, impact ionization caused by a high ${V}_{d}$ generated electron–hole pairs and some holes accumulated under the gate region, which caused the negative shift of the threshold voltage (${V}_{\text{Th}}$), leading to an abnormal increase in ${I}_{d}$ during the reverse sweep. [ABSTRACT FROM AUTHOR]

This study investigates an improvement in memory characteristics through depositing an In2O3 layer as an oxygen ion reservoir in the switching layer (SL) of resistive random access memory (RRAM). The deposition of In2O3, denoted as Pt/HfO2/In2O3/TiN device, provides better memory characteristics including lower forming voltage (VF), set/reset voltage (VSET/VRESET), larger memory window, and higher resistances with higher uniformity at low resistance state (LRS) and high resistance state (HRS), compared to the devices without the In2O3 deposition, denoted as Pt/HfO2/TiN device. The conduction mechanisms, verified through fitting current–voltage (I - V) curves, are consistent with the results of a varied temperature I - V experiment. Finally, a physical model is proposed to explain our observations. [ABSTRACT FROM AUTHOR]

This article explains the difference in the reset processes between single RRAM and 1T1R RRAM structures. In the single RRAM, as the reset voltage increases, the off-state resistance increases. This is a normal RRAM operation. However, in the 1T1R structure, the reset voltage increases while the OFF-state resistance does not increase. This may be caused by either current or voltage being insufficient to switch the RRAM to its higher resistance state. The measurements of real voltage indicate that the insufficient voltage is in fact the main cause. For the 1T1R RRAM structure, if it is to be reset to a higher resistance state, it is best done by increasing the gate voltage to increase the OFF-state resistance. Therefore, we provide a method to reduce the misjudgment in the array, and it would be beneficial for the development of high-density memory. [ABSTRACT FROM AUTHOR]

This paper investigates material modifications induced by cosputtering indium-tin oxide (ITO) with gadolinium (Gd) at two different power levels. In addition, resistance switching (RS) properties were also verified for use as an insulator in resistive random access memory (RRAM). Comparison of scanning electron microscope (SEM) measurements for the two different cosputtering powers indicated significant changes of the ITO surface. Transparency was also verified by an N&K analyzer measurement, with results indicating a constant in transparency induced by the lower power Gd doping, indicating potential for transparent applications. Furthermore, the mole fraction ratio defined by X-ray photoelectron spectroscopy reveals a Gd2O3 peak, a likely reason for the ITO thin film becoming less conductive. This ITO/Gd:ITO/TiN RRAM can exhibit stable and robust RS characteristics at a lower forming voltage. In addition, lower operating voltages, including both SET and RESET voltages, can be obtained. Reliability tests including endurance and retention were carried out to confirm its RS stability. The RS mechanism of this ITO/Gd:ITO/TiN device was also investigated with the current–voltage (${I}$ – ${V}$) fitting method. Moreover, temperature effects were also applied to verify the high-resistance state (HRS) mechanism. Finally, a conduction model was proposed to clarify the RS characteristics and confirm that the ITO/Gd:ITO/TiN device is appropriate for data storage. [ABSTRACT FROM AUTHOR]

In this paper, vanadium oxide (VOx) was chosen for the resistive switching layer in a typical resistive random access memory (RRAM) structure. During negative forming bias, we found an initial selector property. This indicates the presence of metal–insulator-transition characteristics in the VOx layer even without an annealing process. In order to study this phenomenon, material analyses were conducted, with results indicating that there are V-O stretching bonds and an oxide/vanadium ratio of nearly 2.2 (${O}/{V} = {2.2}$). In addition, the experimental results of the dc sweeping test indicated that off-state current gradually decreased after each cycle, meaning that the selectivity characteristics in the VOx selector could be improved. Endurance performance of our experimental devices reached 108, sufficient for integration with RRAM devices in a 1S1R array. To further investigate this special phenomenon, current fitting analysis and simulation analyses were conducted. The results of the fitting analysis indicated that the conduction mechanism for off-state current was Schottky emission and the Schottky distance increased with increasing numbers of cycles. In other words, oxide ions migrate toward the filament at low negative voltage during dc sweeping, causing the formation of VOx. Furthermore, the results of thermal field simulation analysis indicated that there is a thermal concentration effect in and around the filament. Thus, oxide ions more easily migrate toward the vanadium filament when a stronger electrical field is present around the filament during dc sweeping cycles. Finally, stable vanadium selector characteristics are obtained and a conduction filament behavior model is proposed. [ABSTRACT FROM AUTHOR]