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The supply voltage scaling has become increasingly challenging in the advanced CMOS technology due to the threshold voltage requirement for transistor OFF leakage, limiting the system energy efficiency. Spintronic logic utilizes the physical quantity of magnetization or spin as a computation variable, offering new design paradigms in terms of ultralow voltage operation and nonvolatility, but suffering from switching inefficiency of the charge-to-spin conversion. The magnetoelectric spin-orbit (MESO) device has been proposed as a new alternative logic device candidate to solve these issues by magnetoelectric transduction using a novel multiferroic oxide [both ferroelectric (FE) and antiferromagnetic], a ferromagnet and a spin injection layer. It enables a path toward 10-100× switching energy reduction compared to CMOS inverter in 2018 node, due to the device and material innovations of a novel switching mechanism. In this paper, in order to build a MESO logic family for new circuit and architecture exploration, we propose for the first time the fundamental building blocks such as MESO sequential and combinatorial circuits for the synchronous logic operation. We employ a transistor sharing and a novel multiphase clocking scheme to address the circuit design issues such as clock control, directionality of state propagation, and power gating and enable the design exploration for MESO digital logic. Based on the proposed circuit techniques, we demonstrate these MESO logic functions operating at a supply voltage of 100 mV and a clock period of 1.2 ns with 320-ac FE polarization through the circuit simulations.

Reducing VDD while keeping leakage current low is critical for minimizing energy consumption for systems across the compute-continuum, especially in IoT. Emerging low-VDD logic devices such as tunnel FET (TFETs) offer better low-VDD performance than conventional MOSFETs but lack performance at high-VDD. To assess TFETs, and other transistors optimized for low-VDD operation, we propose a technology-driven design framework. Our framework adapts standard industry flows and tools to optimize the design of logic blocks with full consideration of the tradeoffs possible with the future generation device I-V characteristics and interconnect. Proposed approach optimizes design implementation to improve projected power-performance and area, as well as, expected accuracy of the projections. TFET improves energy efficiency by 2.35× and 1.35× over MOSFET at low- and high-performance points, respectively, for industrial design test cases. Accuracy of the energy efficiency and performance projections is improved by 71% and 40%, respectively.

In the above paper [1], the following Acknowledgment was not included.