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An approach for scalable quantum computing infrastructure based on the use of low-power digital superconducting single flux quantum (SFQ) circuits is described. Rather than replicating the room-temperature microwave control and measurement infrastructure solutions dominating the current systems, we use the inherent to superconducting technology methods – the use of SFQ pulses directly at the base temperature. For qubit control, we irradiate qubits with the coherent SFQ pulse sequences computed using optical control theory. For qubit measurement, Josephson photon counter performs projective quantum measurement, the result of which is converted to digital SFQ output. These operations are aided by a high-speed digital SFQ coprocessor located at higher temperature stage (e.g., 3 K) to process the measurement results and load new control sequences to 20 mK SFQ quantum-classical interface circuits.

We present test results for parallel data communication ERSFQ circuits with clock recovery. We experimentally study on-chip and chip-to-chip parallel data communication circuits with 4-, 8- and 16-bit word lengths. The largest circuit is a 16-bit chip-to-chip communication test circuit embedded into a testbed with clock distributed over a combination of active and passive transmission lines with transmitter/receiver pairs, and is comprised of 3464 Josephson junctions in total. All ERSFQ circuits are fabricated using MITLL 10-kA/cm2 SFQ5ee process. For the chip-to-chip communication experiment, a multi-chip module (MCM) is assembled using Hypres' MCM flip-chip bonding process which connected the MIT-LL-made flip-chip to the Hypres-made MCM carrier using 220 signal bumps with 50 um pitch. We experimentally confirmed correct functionality of 4-, 8- and 16-bit circuits and measured their current bias margins. For the 16- bit chip-to-chip communication circuit mounted to a MCM, we measured ±12% dc bias margins similar to the margins measured for the on-chip version of the same circuit. The MCM circuit is also evaluated at high clock speed generated by an external source, while the data words are changed at low speed. The correct functionality is observed without significant reduction in the bias margins using average-voltage test approach.

We develop an energy efficient digital data link connecting cryogenic superconducting single flux quantum (SFQ) circuits to room-temperature electronics. The design is based on low-temperature (4 K) superconductor ERSFQ SFQ/dc drivers, high-temperature superconductor data cables spanning 4 K to 70 K temperature stages, mid-temperature (70 K) polarization modulation vertical cavity surface emitting lasers (PM VCSELs), and fiber optic links to room temperature electronics. The Energy-efficient Cryogenic Optical (ECO) data link design is based on balancing power dissipation and signal gain at each temperature stage to maximize overall energy efficiency following the recently introduced Thermo-Gain Rule. To achieve VCSEL light emission with two switchable distinct polarization modes, a cruciform-shaped anisotropic optical cavity is formed by fabrication of a photonic crystal with etched periodic air holes surrounding the unetched cruciform region. In this report, we present the results of design, fabrication, and preliminary testing of the ECO data link components.

We report on the successful operation of partially depleted silicon on insulator (PD-SOI) ring oscillators at temperatures down to 2.8 K. This 45 nm CMOS technology node hardware was fabricated on 300 mm wafers that were part of a development lot not optimized for low temperature operation. The test structure comprises a set of ring oscillators, an output multiplexer and a divide by 1024 circuit followed by an off-chip driver. By reducing the temperature of the device from 300 K to 2.8 K, the static power dissipation decreases by more than an order of magnitude. Circuit delays improve by approximately 20%, 16% from drive current enhancement and 4% from capacitance reduction. To gain further insight on this behavior we are measuring at cryogenic temperatures single MOSFETs and small arrays of MOSFETs that were fabricated alongside the ring oscillators. Experimental results and potential applications of cryogenic PD-SOI are presented.