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This paper demonstrates the first silicon-verified FBMC encoder and decoder designed to emulate beyond $224Gb/s$ wireline communication. It also compares the performance of FBMC to PAM and DMT in three steps. First, the digital power and area consumption are compared using measured results from the manufactured test chip. Second, the data rate is determined using lab-measured results. And third, the performance when subject to notched channels is analyzed using simulation results. Finally, we present a method to emulate wireline links while reducing the emulator complexity and simulation time by one to two orders of magnitude over conventional over-sampled techniques. Our analysis indicates that given a smooth channel and an SNR which enables an average spectral efficiency of $4bits/sec/Hz$ at a bit-error rate of 10-3, both DMT and FBMC perform similarly to a conventional PAM-4 link. However, when noise is reduced and a spectral notch is applied, thereby achieving an average spectral efficiency of $4.6bits/sec/Hz$ , DMT and FBMC can outperform PAM by 2.1 and 2.3 times, respectively. In addition, we estimate FBMC’s encoder and decoder power consumption at $1.53pJ/b$ and $1.98pJ/b$ , respectively, and area requirement at $0.07mm^{2}$ and $0.17mm^{2}$ , respectively, which is similar to DMT. These values are competitive with similar $22nm$ PAM transceivers, suggesting that DMT and FBMC are viable alternatives to PAM for next-generation high-speed wireline applications.

This paper describes an analog multi-tone receiver capable of processing three data streams running at 15 Gb/s, one in baseband and two in quadrature over carriers at 15GHz, achieving an aggregate rate of 45Gb/s over a single physical channel. The receiver maximizes bandwidth efficiency by using orthogonal sub-channels and avoids the need for analog to digital converters by incorporating a mixedsignal MIMO equalizer that can mitigate inter-symbol interference and inter-carrier interference. The system is designed and laid out in a 22nm FDSOI technology. Post-layout simulations are employed to verify the effectiveness of the proposed architecture, demonstrating a raw BER of 10−5 over a channel with an insertion loss of 14dB at 28GHz is achieved. The complete system has an energy efficiency of 6.6pJ/bit and occupies an active area of 0.29 mm2.

Limits of data rate over a wireline channel depend on the channel characteristics, the signaling or modulation scheme, and the complexity one can afford for its implementation. This article compares two signaling schemes, namely baseband and discrete multi-tone (DMT), for two example channels, one with a smooth frequency response and one with a notch frequency response, to examine how far each can push the data rate towards the maximum achievable data rate, derived from Shannon Capacity formula.