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Oil is a key medium for transmitting power and coupling information in the hydraulic transmission system. Accurate calculation and measurement of the dynamic compressibility of the oil have profound significance to the system performance analysis. The present study primarily focuses on the effect of steady pressure on the bulk modulus of static oil. However, changing pressure and flowing oil are the general working conditions in most of hydraulic apparatus. There are few researchers paying attention to the influence of pressure on the compressibility of flowing oil. Considering the log-normal distribution of bubble size in oil, an improved static oil model (Model B) is developed to calculate the bulk modulus of the motionless oil under the dynamic pressure. Then, by deriving Model B, this paper proposes an original flowing oil model (Model C) to determine the effective bulk modulus of flowing oil. Finally, based on the inherent pressure pulsation of the axial piston pump, an innovative online method for measurement of the bulk modulus of flowing oil is presented as it has the advantage of avoiding interference with flow stability. It has been proved that the changes in the flow velocity corresponds to the crucial effect on the effective bulk modulus of flowing oil, especially under the low-flow and low-pressure operation conditions. Those results and analysis provide promoting support for identifying and determining the effective bulk modulus of oil, analyzing the system stiffness, improving the control accuracy, as well as optimizing the mathematical models.

Dopant-free carrier selective contacts have garnered significant interest for the development of high-efficiency silicon solar cells due to their low-temperature processing and suppression of free-carrier absorption. In this work, we investigate thermally-evaporated molybdenum oxides (MoO x ) functioning as a hole-selective contact (HSC) for silicon heterojunction (Si HJT) solar cells. The high work function of MoO x results in upward energy band bending at the MoO x /n-type Si interface, which facilitates the hole transport and blocks the electron. We compare the optical properties of MoO x with different thickness settings of 3, 10, and 15 nm, where the optical bandgap is fitted via the tauc plot and ranging between 3.46, 3.44, and 3.42 eV, respectively. The absorption spectra of MoO x , MoO x with an intrinsic amorphous silicon (a-Si(i)) layer, and sputtered tin-doped indium oxides (ITO) are also presented. The transmission electron microscopy further reveals a 2.8nm-thick silicon oxides layer in between the MoO x and silicon interface. Preliminary results show that the Si HJT cell with a 15 nm-thick MoO x layer achieves a power conversion efficiency (PCE) of 20.3% and an open-circuit voltage (Voc) of 651.9mV, possibly limited by the pyramidal surface morphology and the a-Si(i) interface passivation layer.

A single-crystal-island (SCI) technique is demonstrated using low thermal budget pulse laser process to fabricate single-crystal islands for monolithic 3D back-end-of-line (BEOL) FinFET circuits. The single-crystallinity are verified with SECCO etch, HREM, TEM, and EBSD. BEOL FinFETs fabricated in the designed single-crystal Si islands exhibit excellent electrical performance and low intra-island variability. To mitigate the effects of island-to-island device variation due to random island crystal orientations, crystal-orientation-tolerant voltage regulator is further proposed by allocating power gating (PG) cells among multiple Si islands, and 42% power noise suppression can be achieved.

This paper demonstrates the first Monolithic 3D+-IC based Compute-in-Memory (CiM) Macro performing massively parallel beyond-Boolean operations targeting database and machine learning (ML) applications. The proposed CiM technique supports data filtering, sorting, and sparse matrix-matrix multiplication (SpGEMM) operations. Our system exhibits up to 272x speedup and 151x energy savings compared to the ASIC baseline.

For the first time, ultrafast laser annealed BEOL gate-all-around (GAA) transistor and FeFET memory were demonstrated with monolithic 3D near-memory-computing (NMC) circuit. The GAA MOSFETs employing ultrafast picosecond visible laser dopant activation exhibit record-high Ion (nFETs=407 uA/um, pFETs=345 uA/um). The BEOL FeFETs memory exhibits large memory window ΔV th = 1.2V, more than 106 cycle endurance. Moreover, the 3D stackability of the GAA MOSFETs and FeFET memory bit cell enable reduces the area of the NMC circuitry and improve the readout throughput.

For the first time, a 3D stacking of MoS 2 and Si CMOS integrated with embedded RRAM is proposed and fabricated, and CMOS inverter comprised of MoS 2 nFET and Si pFET is demonstrated. Vertically stacked multiple MoS 2 channels are required for the performance matching. Resistive switching (RS) of a Ti/MoS 2 /p+-Si structure showing high ON/OFF ratio of 106 is demonstrated firstly by highly Si-compatible process. Surface modification is the key to formation of uniform and smooth stacked MoS 2 multiple channels and to enhanced resistive switching endurance. This scheme can be applied to CMOS-based bipolar RRAM 1T1R or 2T1R without increasing the cell size. Our work offers a new pathway with high feasibility of integrated 2D materials and Si FETs into CMOS to enabling 3D embedded logics and memories for future computing systems.

For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

Vertically Stacked Nanosheet FET (VSN-FET) is considered to be the most promising device to replace FinFET beyond the 3nm node. The VSN-FET can be implemented in either inversion mode (IM) or junctionless mode (JL). In order to reduce the impact of process variations on VSN-FET without sacrificing device characteristics, a new junctionless accumulation mode (JLAM) VSN-FET is proposed in this paper. By using TCAD with a statistical impedance field method (sIFM), the process variations of VSN-FET in IM, JL, and JLAM are compared in terms of RDF, WFV, and OTV. The results show that JLAM-VSN-FET has a simpler process compared to IM-VSN-FET, and better variation immunity compared to JL-VSN-FET. Further simulations of JLAM-VSN-FET indicate that the increase of work function difference in gate metal grains leads to the degradation of σ Vth . Besides, the application of thicker physical gate oxide with higher-κ is confirmed to alleviate σ Vth_WFV . As device scaling down, nanosheet height and gate oxide thickness scaling leads to the reduction of σ Vth_RDF , whereas channel length and width scaling results in the degradation of σ Vth_RDF , σ Vth_OTV , and σ Vth_WFV .

In this paper, for the first time, a vertically stacked silicon nanosheet-FET (VS-NS-FET) based biosensor is proposed and studied by 3D TCAD simulations. Furthermore, a comparative sensitivity analysis with conventional nanowire (NW-FET) biosensor and vertically stacked nanowire (VS-NW-FET) biosensor is performed to evaluate the performance of the device. The results indicate that the variation of the VS-NS-FET biosensor in transfer characteristics for different target biomolecules (with different dielectric constants (at p = 0) and charge densities (at k = 5)) is pronounced. Moreover, the proposed VS-NS-FET biosensor is more sensitive than the other two biosensors due to the increase of the channel width and the stacked structure. This biosensor is a promising candidate for future CMOS-based sensor applications.

A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\ \mathrm{A}/\mathrm{W})$ and tunable photogain (10 2 ~10 5 ) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.

A multi-level state HfO 2 -based resistive switching model is reported, where the increase in stopping voltage (V stop ) and thus activation energy (E AC ) is attributed to the depletion of oxygen vacancy (V o ) concentration (n c ) during reset. Hopping conduction fittings also indicated a depletion of n c due to an increase of V stop as shown by an increase of trap-to-trap distance (a) and trap energy (ϕ T ).

For the first time, below 400°C-fabricated poly-Si MOSFETs and 6T -SRAM fabrication process was demonstrated on polyimide (PI) substrate for flexible and transparent monolithic 3DIC. Key enablers are 400–900 nm transparent laser-stop layer (LsL), laser-crystallized/CMP-thinned poly Si channel and pulse UV-laser S/D activation. These advanced low thermal budget fabrication technologies enable stackable polySi MOSFETs on flexible 6” -wafer-scale PI substrate with high device uniformity $(\mathrm{V}_{\mathrm{th}}$ ‘SS~16.2%/16.6%) and bending stability $(\mathrm{V}_{\mathrm{th}}/\mathrm{SS}\sim 4.2\%/9.8\%)$ after cycle-bending at radius of 10mm. Such CMOS compatible technologies envision flexible 3D heterogeneous integration of circuits/optical sensors for human-skin adaptable Internet of Things (IoT) chips.

In this paper, study on the thermal annealing effect is done on nanoscale W/TaO x /Pt resistive random access memory (RRAM) structure. Electrical characterization shows that device performance is improved after undergoing thermal annealing, with the cycle-to-cycle and device-to-device variability showing less variation with lower operating voltage. The device also undergoes CMOS BEoL compatible thermal budget.

In this paper, conductance switching behavior of Pt/HfOx/Ti redox-based memristive devices has been thoroughly investigated. The conduction mechanisms involved during the device operation can be associated with the trap-controlled SCL conduction mechanisms. The extracted parameters suggest the gradual switching behavior achieved by the devices was due to the transition between different trap level within trap-fill SCL regime, which is beneficial for the device implementation as analog synapse in the neuromorphic computing platform.

For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

For the first time, below 400°C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I on /I off ratio (~108) with low I off (pFETs