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We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits $> 30\%$ CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2nd-year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with $> 10\text{Gbps}$ connectivity.

We present a 5nm logic technology scaling step-up holistic approach for 5-track standard cell design employing electrically gate-all-around nanowire architecture (EGAA NW) with much reduced parasitic capacitance and increased effective width for better short channel control and stronger drive. We suggest SiGe P-channel by Ge Condensation for intrinsic mobility improvement and substrate strain, conformal wraparound contact (CWAC) to reduce contact resistance with minimum parasitic capacitance penalty, metal gate (MG) stressor to improve N-channel mobility, EUV single exposure metal patterning with improved tip-to-tip patterning technique for maximum mask count reduction, and Al metallization to reduce metal & via resistances, however still requiring a validation of the proposed electromigration (EM) risk mitigation. We show that finFET can still be extended to 5nm technology to meet Power-Performance-Area-Cost (PPAC) targets. EGAA NW could enable further 50mV less supply voltage to significantly improve 5nm PPAC scaling.

The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.

Wind and solar power generation are fluctuated and uncertainty. The utility grid will be affected seriously if high ratio wind power is merged. The rapid development of energy storage technology brings to efficient utilization of new energy. This paper introduces an integrated control strategy of smoothing power fluctuations and peak shaving based on HESS (hybrid storage energy system) with super-capacitor and battery. The generated power fluctuations of the wind/photovoltaic (PV)/HESS will be controlled under constraints by low-pass filter. Meanwhile the grid peak load will be shifted by integration power forecasting with storage plan management of future 24 hours. The integrated control strategy can realize the power smooth and load shifting effectively. The feasibility of the control method is verified by MATLAB/SIMULINK.

We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.

We present, for the first time, a holistic data-path driven transistor-interconnect co-optimization method, which systematically isolates the logic-gate and interconnect-wire dominated data-paths in block-level delay-bins (i.e., sub-binning of delay based bins) to significantly improve accuracy of static and dynamic power estimation. It captures the critical interdependence of transistor architecture (FEOL) including local interconnect, and BEOL metal stack optimization to achieve holistic 10nm (N10) technology optimization at target speeds. Using the proposed method, we drive >2.5x Performance/Watt (PpW) improvement for N10 FinFET SOC design over 14nm (N14). Even with ∼3x higher wire resistance of min metal width, the PpW @target-speed for N10 improves >2.5x over N14 with proper design of metal/via stack, transistor Vt and fin-profile as well as standard-cell architecture. Reducing active fin-count and routing distance between standard-cells is a critical design knob for N10 mobile SOC enablement. The proposed methodology enables smartphone-usage (days-of-use) based technology optimization, driving longer battery-life in mobile SOCs, keeping process cost and complexity at minimum.

We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (R wire ) multiplied by logic gate input pin cap (C pin ), R wire ×C pin , is identified as a major limiter of performance and power at N7. Reducing C pin is crucial to mitigate abruptly rising BEOL R wire effect. Depopulation of fin is one of most effective methods to reduce C pin , and scale the logic gate area. Air Spacer (AS) on transistor sidewall is proposed to further reduce C pin , whose benefit is enhanced by reduction of other C pin components. Careful choice of routing metal stack ameliorates adverse effect of R wire . Wrap-Around-Contact (WAC) over Source and Drain of scaled fin pitch (P fin ) is needed to reduce transistor resistance (R tr ). Fin depopulation with other cost effective process innovations significantly improve Power-Performance-Area-Cost (PPAC) of N7, enabling continued scaling of mobile System on a Chip.

We report for the first time a highly selective CVD Co deposition on Cu to fill a 45nm diameter 3:1 aspect ratio via in a Cu dual damascene structure. We have achieved void-free Co fill of the via, demonstrating that a selective bottom-up via fill with Co is a potentially viable approach. Defect formation and control in the process and device integration are discussed. This selective process provides an opportunity to reduce via resistance and shrink the minimum metal 1 (M1) area for aggressive standard cell size scaling as needed for 7nm technology.

A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.

The main task of a mobile robot is to perform navigation and orientation. In this paper, a navigation method for three-wheel mobile robot is introduced based on interactive force information. The interaction force information between mobile robot and wall or unknown obstacle comes from the robot end effector, which may be a multi-DOF manipulator with force sensors or an antenna using the elastomeric material. Considering complexity of the structural, difficulty of the system control and the low-efficiency of this method, the system can obtain collision information using multi-dimension force sensors fixed on mobile robot body. Its aim is to complete the survey, self-localization and the path programming, and it is a good supplement to existing navigation methods such as the image, light, electromagnetism, sound. The experimental results indicate the validity of this method using interactive information to estimate relative position/orientation to an unknown object.