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An active bidirectional mixer performing the up/down conversion has been proposed at K band with a 130-nm CMOS in this paper. With 2-dBm local oscillator drives, the mixer achieves the conversion gain, noise figure, and output P ldB of −2.5~-1.2 dB, 14.2~16 dB, and −9.2~-8 dBm from 23 to 25 GHz in up-conversion mode, respectively. In down-conversion mode, the mixer exhibits the conversion gain, noise figure, and input PldB of 1.3~3 dB, 15.2~19.3 dB, and −0.6~0 dBm from 23 to 25 GHz, respectively. The chip area is 0.75 × 0.8 mm2, which consumes 10.5 mW from a supply of 1.5 V.

Path Planning Problem is very hard for its huge search space. In this paper, we quote the definition of homotopy in mathematics to describe the right "direction" of the optimal path, which is a necessary condition for the optimal paths under the holonomic condition. Based on the concept of homotopy, optimal homotopy property is proposed for paths. Numerical experiments involving RRT*, sPRM, RRT, PSO, A* and Jump Point Search (JPS) are carried out. Although A* and JPS are gird space optimal, these do not satisfy optimal Homotopy property.

In this paper, the problem of finite-time fault detection (FD) is investigated for networked discrete-time singularly perturbed systems under the stochastic communication protocol (SCP). To alleviate the undesired data collisions caused by large-scale data transmissions via the bandwidth-limited communication network, the SCP modeled by a Markov chain is introduced. Due to practical factors such as observation error, the Markov modes of the SCP are assumed to be available to the fault detection filter (FDF) according to a hidden Markov process. Our aim is to design a hidden-Markov-model-based FDF as the residual generator such that the resulting augmented system is stochastically $H_{\infty}$ finite-time bounded. A sufficient condition in terms of linear matrix inequalities (LMIs) is derived which ensures the existence of such an FDF. The parameters of the desired FDF are explicitly given when there exist feasible solutions to these LMIs. Finally, the effectiveness of the FD method is demonstrated by a numerical example.

This paper presents a fully integrated 166-GHz frequency synthesizer (FS) in 0.13-μm SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler (×2) and a quadrupler (×4). The FS generates the D-band output signals from 164.08 to 166.19 GHz. At 166.19 GHz, the measured phase noises at 100-kHz and 1-MHz offset frequencies are −54.07 dBc/Hz and −72.29 dBc/Hz, respectively. The total dc power dissipation of the FS is around 110 mW and the chip area is 2.16 × 0.57 mm2 including all testing pads. To the best of authors' knowledge, the proposed FS achieves the lowest power dissipation above 100 GHz to date and has great potential to be used for high-integration D-band applications.

This paper presents a 340 GHz 4-way fully integrated phased array transmitter using 0.13um SiGe BiCMOS technology. The chip integrates a 21.25 GHz synthesizer, a quadrupler together with a 1:4 Wilkinson network, power amplifiers, analog phase shifters, 20Gbps OOK modulators, and 2×2 on-chip antenna arrays on each channel. Simulated patterns show scanning to ±12° and >12dBi gain in E-plane. The chip size of the fully integrated phased array transmitter is 8×4.3 mm2.

A 8-12 GHz fully monolithic transformer-coupled cascode power amplifier (PA) with the chip size of 2 × 2 mm2 fabricated using the 0.25-μm SiGe:BiCMOS technology is presented in this paper. Through circuit/layout co-design, the distributed capacitor structure which is connected to the base of cascode transistor is proposed to reduce the base connection inductance for solving circuit instability and improving the gain in the design. Moreover, the PA features a three-stage cascode architecture that includes both high-speed (low breakdown voltage) and high breakdown voltage (low-speed) SiGe transistors. The proposed PA attained a measured small signal gain of 27.6-29.6 dB from 7.7 to 12 GHz with a 5.0 V dc supply. A 28 dBm maximum output power with an 18.5% power-added efficiency at 10 GHz have also been achieved.

A 20-GHz voltage-controlled oscillator (VCO) for phase-locked loop (PLL) synthesizer is presented in this paper. The VCO and PLL synthesizer have been implemented using only CMOS devices of a 0.13-μπι SiGe BiCMOS technology with the chip area of 0.22 mm2 and 0.48 mm2, respectively. The measured tuning range of the VCO is 2.21 GHz from 19.9 to 22.11 GHz; the PLL synthesizer can generate output frequencies from 20.51 to 21.27 GHz successfully and the measured phase noise at 100-kHz and 1-MHz offset frequencies is −68.66 dBc/Hz and −97.17 dBc/Hz, respectively. At a 1.5-V supply, the power dissipation of the VCO and PLL synthesizer is 27 mW and 40 mW, respectively.

Wideband directional couplers with high isolation are designed for millimeter-wave applications and implemented in two different in-house Si-based technologies processes — Si-benzocyclobutene (Si-BCB) process and LIGA-like process (lithography, electroplating, and molding). Two 3D tandem directional couplers for millimeter-wave/THz applications have been constructed using the Si-BCB process. The coupling and isolation of tandem coupler have been analyzed from circuit topology. A branch-line coupler is also constructed using the LIGA-like process. The electrical characteristics of these couplers have been simulated in 3D simulator. By comparing the results, the proposed Si-BCB process is noted to provide flexibilities in both the design and implementation of passive components.

This paper presents a comprehensive analysis of the electrical performance of the bonding-wire interconnection up to 170 GHz. The effects of the wire length, loop height and pad area have all been analyzed. An electrical model for the bonding-wire is discussed. By reducing interconnection distance and optimizing pad area, the performance of the bonding-wire can be enhanced. The acceptable measurement results of the bonding-wire up to 170 GHz are obtained.

In this paper, a novel 60 GHz flip-chip bandpass filter in standard CMOS technology is proposed. An insertion loss of 0.69 dB/mm for microstrip line is obtained at 60 GHz by using cascaded THRU de-embedding method. By deploying the gap between the flip-chip bump and the flipped chip, an endcoupled, half-wavelength resonator filter is designed and fabricated. The measured insertion loss of 3.3 dB and return loss of >13 dB with a bandwidth of 63% at centre frequency of 60 GHz clearly demonstrates that the proposed flip-chip filter is a promising candidate for 60 GHz integrated circuits applications.

In this paper, an improved correlation method is proposed to detect the phase difference between two signals in high frequency in a polarimetric radar system. The mean value of the correlation of two sampled signals is calculated based on Field Programmable Gate Array (FPGA) to give a more accurate result of the detection. The method is simulated in Simulink®, and the blocks are then converted into a Quartus II project and compiled to show the occupied resources. The basic principle of the method is described in detail and the results of the simulation provide some evidences that the method can be applied in the radar system for real time processing. Some notes are also given to improve the performance in practical applications.

Compact open-loop resonators loaded by open stubs are used to design cross-coupled filters with a dual-passband response of chebyshev function. The second passband of the proposed filter is obtained by tuning higher resonant modes of the open-loop resonator by changing the stub length and position. Proper couplings required for the two desired/designed frequencies are obtained by tuning the relative open position of open-loop resonator and the distance between the resonators. Required external coupling is obtained by adjusting the tapping position and dual-frequencies transformer. The S-parameter of the dua-passband filter has been measured. The results show good agreement with the simulation ones. Furthermore, the proposed filter has two transmission zeros and exhibits high skirt selectivity.