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A clock tree synthesis (CTS) has become a crucial step in a high performance synchronous system. Clock gating technique is an efficient method for reducing power consumption. However, it unevenly impacts negative bias temperature instability (NBTI)-induced Vth degradation of clock buffers. Thus, it may cause asymmetric aging resulting in a large clock skew. In this work, we propose a novel symmetrical buffered clock tree synthesis with supply voltage alignment for handling NBTI. Our CTS estimates asymmetric NBTI caused by clock gating through signal probability. We formulate the skew minimization problem based on linear programming which determines optimal SVs of buffers. Then, we align supply voltages (SVs) on buffers while satisfying skew constraints after years of aging. Wire routing is performed using wire snaking to complete the clock tree. Experiment results show that the proposed CTS achieves on average 35.5% reduction in clock skew compared to existing CTS methods after 10 years of NBTI degradation.

As CMOS technology continuously scales down, robust clock tree synthesis (CTS) has become increasingly critical in high-performance synchronous chip design. Recently, the process variation during manufacturing affects the performance of the circuit design. In this paper, we proposed fast buffered clock tree synthesis (FBCTS) in multi-corner multi-mode (MCMM) scenario. The ISPD '09 benchmark is used to verify the proposed method. The experiment results show our method reduce about 59% of computation time compared to existing method.

Clock tree synthesis (CTS) is a critical part on the total performance of chip. Buffer insertion is required in clock tree to prevent signal degradation and satisfy slew constraints. Also, buffer sizing minimizes power and skew in clock tree network. In this paper, we proposed slew-aware fast buffer insertion/sizing methodology in CTS based on DME to meet the skew constraints. The experiment results show the proposed sizing method reduce about 13.47% power consumption and 49.03% runtime compared to LP-based method.

A distance cartogram (DC) is a technique that alters distances between a user-specified origin and the other locations in a map with respect to travel time. With DC, users can weigh the relative travel time costs between the origin and potential destinations at a glance because travel times are projected in a linearly interpolated time space from the origin. Such glance-ability is known to be useful for travelers who are mindful of travel time when finding their travel destinations. When constructing DC, however, uneven urban traffic conditions introduce excessive distortion and challenge user intuition. In addition, there has been little research focusing on DC's user interaction design. To tackle these challenges and realize the potential of DC as an interactive decision-making support tool, we derive a set of useful interactions through two formative studies and devise two novel techniques called Geo-contextual Anchoring Projection and Scalable Road-network Construction. We develop an interactive map system using these techniques and evaluate this system by comparing it against an equidistant map (EM), a widely used conventional layout that preserves the geographical reality. Based on the analysis of user behavior and qualitative feedback, we identify several benefits of using DC itself and of the interaction techniques we derived. We also analyze the specific reasons behind these identified benefits.

Continuous scaling of CMOS technology suffers from severe leakage current. Fin-type field effect transistor (FinFET) is an alternative to overcome scaling challenge. The shift from 2D planar to 3D transistors enables greater density, lower power consumption, and higher performance. The delay/power optimization framework for FinFET based circuit using TILOS-like gate sizing is presented in this paper. Utilizing unique feature of FinFET based circuit. The TILOS-like sizing algorithm is used to optimize delay and power in 3D FinFET circuit. The proposed method considers three operating modes of FinFET logic gate for optimization. The ISCAS85 benchmark circuit with 32nm FinFET PTM model is applied to verify our method. In the experiment the power of the tested circuit is reduced by 12.99% in average while minimizing delay.

Nowadays location based techniques are used various fields such as traffic navigation, map services, etc. Because people spend a lot of time in the indoor place, it is important for users and service providers to get exact indoor positioning information. There are many technologies to get indoor location information like Wi-Fi, Bluetooth, Radio Frequency Identification (RFID), etc. In spite of importance of IPS, there is no standard for IPS techniques. In addition because of characteristic of data, security and privacy problems become issue. This paper introduces the IPS techniques and analyzes each IPS techniques in terms of cost, accuracy, etc. Then introduce related security threats.

As CMOS technologies are scaled down into the nanometer range, effects of process variation have increased. Finding a critical path is important for performance and optimization of circuit. In this paper, we proposed efficient K-critical path detection in Multi Corner Multi Mode Static Timing Analysis(MCMM STA). We analyzed the characteristic of circuit and used MCMM timing model for considering various corners and modes. Using this timing model and pruning method, we can find more efficiently K-critical paths than traditional STA.

Different microRNA target prediction tools produce different results. Motivated by this fact, here we present an ensemble-learning approach that combines the outcomes from multiple tools to reduce prediction error. We test this approach with a dataset derived from a public database containing human microRNAs and microRNA-mRNA pairs. According to our experimental result, using the proposed method tends to be significantly better than using individual prediction tools in terms of increasing the area under curve (AUC) defined on a receiver operating characteristic curve.

New threats to embedded systems have appeared lately and attacks such as physical hacking using high cost analysis tools have become popular. This is the reason why hardware component of devices managing confidential information cannot be considered as trusted anymore. In this paper, we propose a confidential data protection scheme from physical hacking. Our proposal provides encryption of confidential data stored in external memory with additional features such as anti key analysis/cloning and key destruction mechanisms.

Negative bias temperature instability (NBTI) has become a major factor of reliability. In this paper, we proposed a simple analytical model to predict the degraded delay distribution due to NBTI and process variation. Using our NBTI and variation-aware timing analysis framework, accurate degraded gate delay is computed without tedious simulation. Moreover, conventional variation-aware design techniques can apply to develop a reliable circuit design using our model.

Wireless sensor networks are used in many applications in military, ecological, health, and other areas. These applications often include the monitoring of sensitive information making the security issue one of the most important aspects to consider in this field. However, most of protocols optimize for the limited capabilities of sensor nodes and the application specific nature of the networks, but they are vulnerable to serious security attacks. In this paper, a Secure Energy and Reliability Aware data gathering protocol (SERA) is proposed, which provides energy efficiency and data delivery reliability as well as a security scheme giving protection against the most common network layer attacks such as spoofed, altered, or replayed routing information, selective forwarding, sinkhole attacks, Sybil attacks, wormhole attacks, HELLO flood attacks, and acknowledgment spoofing attacks.

Conventional cell characterization does not consider Multiple Input Switching (MIS). Since the impact of MIS on gate delay variation is large, it is not possible to predict the accurate gate delay with the conventional cell characterization. We observed maximum 46% difference in gate delay due to MIS. In this paper, we propose a gate delay model considering the delay variation caused by temporal proximity of MIS. The proposed model calculates the delay variation using the Radial Basis Function (RBF). The experimental results show that the proposed method can more accurately predict gate delay when MIS occurs.

This As manufacturing technology scales to smaller dimensions, wire size is increasing and spacing between wires is decreasing, the influence of interconnect becomes dominant factor. Coupling capacitance between wires induces crosstalk. Crosstalk causes functional and temporal problem. In this paper, we propose timing window shift method considering multi-aggressors to reduce delay degradation. We assume that crosstalk induced delay degradation is proportional to coupling capacitance and timing window overlap. In this assumption, we model Aggressive Factor which represents the amount of crosstalk induced delay degradation. Proposed method is experimented with ISCAS85 benchmark circuit. We have a result that average of 4.85% crosstalk induced delay degradation minimization.

Statistical static timing analysis(SSTA) is an emerging technique that addresses increasing process variation effects on circuit behavior for designs at 65 nm and below. SSTA offers a number of advantages over traditional corner based static timing analysis(STA), most notably it provides a more realistic estimation of timing relative to actual silicon performance. Accurate statistical timing analysis needs accurate statistical cell models, which in turn requires a new approach to cell library characterization. A statistical cell characterization system must adequately capture the effects of variation, while simultaneously maintaining fast turnaround time to avoid being the bottleneck in the statistical analysis flow. In this paper, we review various issues in statistical timing analysis. We also describe an efficient library characterization methodology which can reduce the time needed to construct statistical cell library using interpolation.

As technology progresses, power supply noise, such as IR-drop and L*di/dt drop, has become a major concern in power distribution network design. Since power supply noise is fundamentally caused by large current peaks, it can be minimized in early stages by deliberate clock scheduling which utilizes nonzero clock skew and does not violate timing constraints. In this paper, we propose a clock skew scheduling method to reduce power supply noise by minimizing the peak current. While previous approaches require extra characterization efforts to estimate supply current waveform of circuits, we approximate gate-level current waveform only with existing cell library information. Experimental results show that our method can reduce the peak current by 11.6% on average and the voltage variation in power lines by 18.3% on average.

A numerous property and information are transferred to electronic and computerized while internet and networks are expanded. Behind the convenience, problems such as cyber terror, computer crime, and privacy trespassers are growing constantly. There are a number of evidences showing that damaged computers and the related systems are used for tracking the criminal or proving the crime. In the part of computer forensics, there have been many efforts to find the evidences in the network. A new efficient network forensic analysis using visualization, that supports panoramical views and human centralized analysis is proposed in this paper. In this work, the emphasis on maximizing the visualization effect related to network components is made to build more efficient forensic system. The experimental results show that visualized network forensic analysis utilizes resource and time more efficiently compared to the traditional methods.

A new power optimization by stochastic glitch estimation and removal is proposed in this paper. As the first step of our method, glitch occurrence probability is computed using statistical static timing analysis considering path correlation. Then, path balancing by resizing is applied to remove glitches that are unnecessary signal transitions.

As the integrated technology develops we can design the circuit with thousands of transistors. A hierarchical design Is unavoidable because of a huge circuit size. It is more important how we can consider hierarchically meaningful structure in circuit delay analysis. We computed more accurately the delay of circuit by adding the notation global false path to a previous hierarchical timing analysis. This paper presents the hierarchical timing analysis approach using functional relations considering global false path. Our algorithm utilizes the global false path, the functional relations between the modules. Therefore, the more accurate circuit delay can be obtained than the previous approach. Our algorithm is applied to ISCAS'85 benchmark circuits and carry skip adder. Our experimental results verify that the proposed algorithm is very effective for calculating the circuit delay.

One of the major factors contributing to the power dissipation in CMOS digital circuits is the switching activity. Many of such switching activities include spurious pulses, called glitches. In this paper, we propose a new method of glitch reduction by gate freezing, gate sizing, and buffer insertion. The proposed method unifies gate freezing, gate sizing, and buffer insertion into a single optimization process to maximize the glitch reduction. The effectiveness of our method is verified experimentally using LGSynth91 benchmark circuits with a 0.5/sup um/ standard cell library. Our optimization method reduces glitches by 65.64% and the power by 31.03% on average.

Coupled line switching can contribute to a large portion of the delay as well as the functionality of a circuit. In order to fix a crosstalk noise in noise analysis, it is necessary an additional design cost. Therefore, aggressor nodes that cannot affect victim node have to pruning. In this paper, we present an efficient false aggressor pruning algorithm with functional correlation. Path sensitization algorithm and logic implication approach that use functional information to identify false coupling interaction between coupled lines. Our experimental results show an average of 5.4% aggressor pruning and 14.6% delay reduction due to pruning.

Coupled line switching can contribute to a large portion of the delay as well as the functionality of a circuit. In order to fix a crosstalk noise in noise analysis, it is necessary an additional design cost. Therefore, aggressor nodes that cannot affect victim node have to pruning. In this paper, we present an efficient false aggressor pruning algorithm with functional correlation. Path sensitization algorithm and logic implication approach that use functional information to identify false coupling interaction between coupled lines. Our experimental results show an average of 5.4% aggressor pruning and 14.6% delay reduction due to pruning.

In the circuit model where outputs are latched and input vectors are successively applied by the same clock, the gate resizing approach to reduce the delay of the critical path may not improve its performance. In addition, the gate selection for resizing in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and vice versa. These new gate selection methods prevent the delay of the longest sensitizable path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. Our algorithms are tested on ISCAS85 benchmark circuits and experimental results show that the clock period can be optimized efficiently with our gate selection methods.

Signal flow directions and synchronizers in switch-level circuits are useful information in both simulation and timing analysis. Since signal flow of a transistor may get changed at different clock phases, our new approach of assigning signal flow directions incorporates with synchronizers. Our algorithm takes a global approach by assigning signal flow directions and synchronisers of transistors simultaneously from the graphical representation of a circuit. In our approach, functionality of a circuit is considered to determine signal flow directions, synchronizers, and feasible transitions. Our experimental results show that our algorithm is effective in both static and dynamic CMOS circuits with reasonable time and space.

This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.

Computer-aided design of integrated circuit on the Internet explores new frontiers in the design environment. A new hypermedia CAD system is introduced in this paper promoting distributed design collaboration, remote command executions, and automatic exchange of design data. The proposed organization is implemented using the World Wide Web and the client server communication protocol. The security has been a problem in exchange of data through the Internet. The proposed CAD system alleviates the security problem using the combined system of One-Time Password (OTP) and the RC4 encryption algorithm. Our system is fast and reliable enough to design and provide electronic commerce services of intellectual property blocks on the Internet.