442 results on '"Kaczer, B."'
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2. Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions
3. A Comprehensive Cryogenic CMOS Variability and Reliability Assessment using Transistor Arrays
4. On The Contribution of Secondary Holes in Hot-Carrier Degradation – a Compact Physics Modeling Perspective
5. Reliability challenges in Forksheet Devices: (Invited Paper)
6. Using dedicated device arrays for the characterization of TDDB in a scaled HK/MG technology
7. The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper)
8. Analysis of TDDB lifetime projection in low thermal budget HfO2/SiO2 stacks for sequential 3D integrations
9. Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs
10. Characterizing and Modelling of the BTI Reliability in IGZO-TFT using Light-assisted I-V Spectroscopy
11. Low thermal budget PBTI and NBTI reliability solutions for multi-Vth CMOS RMG stacks based on atomic oxygen and hydrogen treatments
12. New insights on the excess 1/f noise at cryogenic temperatures in 28 nm CMOS and Ge MOSFETs for quantum computing applications
13. Degradation mapping of IGZO TFTs
14. Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions
15. Dedicated ICs for the Characterization of Variability and Aging Studies and their Use in Lightweight Security Applications : Invited paper
16. Analysis of BTI in 300 mm integrated dual-gate WS2 FETs
17. Insight to Data Retention loss in ferroelectric Hf0.5Zr0.5O2 pFET and nFET from simultaneous PV and IV measurements
18. A comprehensive variability study of doped HfO2 FeFET for memory applications
19. Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets
20. Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors
21. Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery
22. Modelling ultra-fast threshold voltage instabilities in Hf-based ferroelectrics
23. Trap-polarization interaction during low-field trap characterization on hafnia-based ferroelectric gatestacks
24. Understanding and modelling the PBTI reliability of thin-film IGZO transistors
25. Evidence of Tunneling Driven Random Telegraph Noise in Cryo-CMOS
26. Low-temperature atomic and molecular hydrogen anneals for enhanced chemical $\mathbf{SiO}_{2}$ IL quality in low thermal budget RMG stacks
27. Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper
28. A BSIM-Based Predictive Hot-Carrier Aging Compact Model
29. Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
30. CV Stretch-Out Correction after Bias Temperature Stress: Work-Function Dependence of Donor-/Acceptor-Like Traps, Fixed Charges, and Fast States
31. Implication of Channel Percolation in Ferroelectric FETs for Threshold Voltage Shift Modeling
32. Atomic Hydrogen Exposure to Enable High-Quality Low-Temperature SiO2 with Excellent pMOS NBTI Reliability Compatible with 3D Sequential Tier Stacking
33. Physical Modeling the Impact of Self-Heating on Hot-Carrier Degradation in pNWFETs
34. Probing the Evolution of Electrically Active Defects in Doped Ferroelectric HfO2 during Wake-Up and Fatigue
35. Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures
36. The Mysterious Bipolar Bias Temperature Stress from the Perspective of Gate-Sided Hydrogen Release
37. Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS)
38. Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications
39. Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures
40. On the impact of mechanical stress on gate oxide trapping
41. First–Principles Parameter–Free Modeling of n– and p–FET Hot–Carrier Degradation
42. Physical Insights on Steep Slope FEFETs including Nucleation-Propagation and Charge Trapping
43. Understanding and Physical Modeling Superior Hot-Carrier Reliability of Ge pNWFETs
44. Impact of Charge trapping on Imprint and its Recovery in HfO2 based FeFET
45. HfZrO Ferroelectric Characterization and Parameterization of Response to Arbitrary Excitation Waveform
46. Statistical Characterization of BTI and RTN using Integrated pMOS Arrays
47. Impact of Charge Trapping and Depolarization on Data Retention Using Simultaneous P – V and I – V in HfO₂-Based Ferroelectric FET.
48. Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics.
49. Low Thermal Budget Dual-Dipole Gate Stacks Engineered for Sufficient BTI Reliability in Novel Integration Schemes
50. New Insights into the Imprint Effect in FE-HfO2 and its Recovery
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