240 results on '"Kaczer, Ben"'
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2. Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper
3. Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing.
4. Discussion Group II – Circuit Reliability
5. Summary of Tutorials
6. On Superior Hot Carrier Robustness of Dynamically-Doped Field-Effect-Transistors
7. Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs
8. Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors
9. A Ring-Oscillator-Based Degradation Monitor Concept with Tamper Detection Capability
10. Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress
11. Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB
12. Impact of Externally Induced Local Mechanical Stress on Electrical Performance of Decananometer MOSFETs.
13. Single- Versus Multi-Step Trap Assisted Tunneling Currents—Part II: The Role of Polarons.
14. On the Modeling of Polycrystalline Ferroelectric Thin Films: Landau-Based Models Versus Monte Carlo-Based Models Versus Experiment.
15. Physics-based device aging modelling framework for accurate circuit reliability assessment
16. The properties, effect and extraction of localized defect profiles from degraded FET characteristics
17. LaSiO x - and Al 2 O 3 -Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration.
18. Cumulated charging mechanisms at gate processing in high-κ first planar NMOS devices
19. Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part I: Theory.
20. Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part II: Experimental.
21. Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation
22. The Influence of Gate Bias on the Anneal of Hot-Carrier Degradation
23. A Compact Physics Analytical Model for Hot-Carrier Degradation
24. A physics-aware compact modeling framework for transistor aging in the entire bias space
25. On Correlation between Hot-Carrier Stress Induced Device Parameter Degradation and Time-Zero Variability
26. Reliability in Stacked Gate-All-Around Si Nanowire Devices: Time-Dependent Variability and Full Degradation Mapping
27. Stochastic Modeling of Hot-Carrier Degradation in nFinFETs Considering the Impact of Random Traps and Random Dopants
28. Hot-Electron-Induced Punch-Through (HEIP) Effect in p-MOSFET Enhanced by Mechanical Stress.
29. Trigger-when-charged: a technique for directly measuring RTN and BTI-induced threshold voltage fluctuation under use-Vdd
30. Full (V-g, V-d) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs
31. Investigation of the Impact of Hot-Carrier-Induced Interface State Generation on Carrier Mobility in nMOSFET.
32. Modeling of Repeated FET Hot-Carrier Stress and Anneal Cycles Using Si–H Bond Dissociation/Passivation Energy Distributions.
33. Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling
34. Full ($V_{\mathrm{g}},\ V_{\mathrm{d}}$) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs
35. Understanding the intrinsic reliability behavior of $\boldsymbol{n}$ -/$\boldsymbol{p}$-Si and $\boldsymbol{p}$-Ge nanowire FETs utilizing degradation maps
36. A Physically Unclonable Function with 0% BER Using Soft Oxide Breakdown in 40nm CMOS
37. Improved PBTI reliability in junction-less nFET fabricated at low thermal budget for 3D Sequential Integration
38. Distribution Function Based Simulations of Hot-Carrier Degradation in Nanowire FETs
39. Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration.
40. Investigation of the Impact of Externally Applied Out-of-Plane Stress on Ferroelectric FET.
41. Extraction of Statistical Gate Oxide Parameters From Large MOSFET Arrays.
42. Special Issue on Reliability.
43. Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach.
44. A Physically Unclonable Function Using Soft Oxide Breakdown Featuring 0% Native BER and 51.8 fJ/bit in 40-nm CMOS.
45. Defect spectroscopy from electrical measurements: a simulation based technique
46. Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices
47. Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects
48. BTI reliability and time-dependent variability of stacked gate-all-around Si nanowire transistors
49. BTI reliability of InGaAs nMOS gate-stack: On the impact of shallow and deep defect bands on the operating voltage range of III-V technology
50. Probing defects generation during stress in high-κ/metal gate FinFETs by random telegraph noise characterization
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