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Data retention (a time-variant characteristic of 3-D- NAND flash memory) is predicted through a bi-directional long short-term memory (LSTM) neural network (NN) model that learns sequential data obtained from chip measurements of a triple-level cell (TLC). The predicted results for all time points of each program (PGM) state are accurately predicted by the threshold voltage (${V}_{\text {th}}$) distribution. Thus, the predicted ${V}_{\text {th}}$ can be used to analyze the cause of retention failure. When the ${V}_{\text {th}}$ of the target cell is high or when that of the adjacent cell is small, the ${V}_{\text {th}}$ loss of the target cell is large. In addition, the ${V}_{\text {th}}$ loss increases as the ${V}_{\text {th}}$ of the adjacent cell decreases. Using a fully calibrated TCAD simulation, we verify the NN-based ${V}_{\text {th}}$ prediction by checking the change in the electron concentration in the nitride layer. Furthermore, the NN model predicts the ${V}_{\text {th}}$ for cells existing in other blocks, showing that they are consistent with the measured ${V}_{\text {th}}$. The prediction times were 5 $\times \,\,10^{{5}}$ s, 5 $\times \,\,10^{{6}}$ s, and 2 $\times \,\,10^{{6}}$ s, but using machine learning (ML), we reduced the time required to predict the ${V}_{\text {th}}$ to only 2 s. Therefore, the proposed ML method enables fast, accurate, and effective predictive modeling of the time-variant ${V}_{\text {th}}$ of 3-D TLC NAND flash memory. Finally, the predicted ${V}_{\text {th}}$ can be included in the read retry table or included in the lookup table of the compensation circuit in NAND solutions. This can save a significant amount of time that would otherwise be spent on actual long-term measurements. [ABSTRACT FROM AUTHOR]

Retention characteristics of 3D NAND Flash cells are investigated at various temperatures (${T}$) depending on the degree of program and erase. The $\Delta {V}_{\text {th}}$ for each condition is compared to understand the degradation of the retention characteristics attributable to vertical loss and/or lateral diffusion. In addition, the relationship between Program/Erase (PE) window (PGM ${V}_{\text {th}}$ – Erase ${V}_{\text {th}}$) and $\Delta {V}_{\text {th}}$ are analyzed. In the case when PGM ${V}_{\text {th}}$ is the same, the $\Delta {V}_{\text {th}}$ decreases as the PE window decreases. At temperatures below 150 °C, $\Delta {V}_{\text {th}}$ and PE window show linear relationship, and as PE window decreases, $\Delta {V}_{\text {th}}$ also decreases to 0. On the other hand, at 250 °C, $\Delta {V}_{\text {th}}$ has a non-zero value even if PE window decreases to 0, thus has a non-linear relationship. The measurement results show that the lateral diffusion has a great influence on the short-term retention of 3D NAND flash cells. [ABSTRACT FROM AUTHOR]

The effect of band engineering by controlling nitrogen content in the tunneling dielectric of the 3-D NAND flash cells is investigated by comparing various cell properties of the two devices. These measured devices have the same device dimensions and different nitrogen contents. The device with higher nitrogen content shows larger trap density profile and improved erase characteristics. After the same P/E cycling stress, the device with higher nitrogen content shows larger increase of trap density and more significant degradation in its erase characteristics. The electrons stored in the device with higher nitrogen content more easily escape through the trap-assisted tunneling mechanism due to higher trap density, resulting in worse retention characteristics at room temperature. [ABSTRACT FROM AUTHOR]

The origin of two different hysteresis pheno- mena observed in a few cells of 3-D NAND flash memory with a tube-type poly-Si body was analyzed. To identify the origin, we analyzed the capture and emission property of charges in two different trap sites by measuring devices at various temperature conditions and using fast I–V measurement. It was found that the clockwise hysteresis property is originated from the traps in the tunneling oxide butted to tube-type poly-Si body and the counter-clockwise hysteresis property is originated from the traps in the high- k blocking dielectric. Although the number of abnormal cells with a large hysteresis is much smaller than that of the normal cells, it is confirmed by pulse measurement that these abnormal cells can produce large threshold voltage variations. [ABSTRACT FROM AUTHOR]

A positive feedback (PF) mechanism was adopted for the first time in the cell string of a 3-D NAND flash memory where n+ and p+ regions are formed on both ends of the string to implement a diode-type cell string. The body consists of a tube-type poly-Si channel. To generate the PF in the channel during a read operation, a new read operation scheme is proposed. In this paper, the simulator was calibrated in terms of trap density ( D\mathrm {it}) of a poly-Si channel extracted from fabricated 3-D NAND flash memory cells. By utilizing the PF, a NAND flash memory cell in a cell string has a steep subthreshold swing of <1 mV/decade. [ABSTRACT FROM AUTHOR]

The trap density ( Nt ) in nitride storage layer of 3-D NAND flash memory cells with tube-type channel structure is extracted. To extract Nt profile in the nitride layer, retention characteristics, and ac-transconductance ( \textgm ) method are used, and equations are derived in cylindrical coordinate. The Nt profile at EC- ET smaller than 1 eV is extracted using retention characteristics of the cells measured at high temperature. The peak value of extracted Nt is \sim 1 \times 10^\mathbf 19 cm ^\mathbf -3 eV ^\mathbf -1 at a EC-ET of 0.93 eV. AC- gm method is used to profile the Nt in EC-ET higher than 1 eV. Extracted Nt profile shows a reasonable continuity between both approaches and looks like a Gaussian function. [ABSTRACT FROM AUTHOR]

A new method to extract the interface trap density ( N \mathrm {\mathbf {it}} ) on the surface of the Si region between adjacent wordlines (WLs—called space region) in nand flash devices is presented in this letter. The \boldsymbol N \mathrm {\mathbf {it}} is successfully extracted by applying charge pumping (CP) method, TCAD simulation, and modified equations. The CP current I \mathrm {\mathbf {CP}} of single WL and electrically tied two WLs are measured using fixed-base CP measurement as a function of pass bias. In addition, an effective space area for CP is extracted by TCAD simulation, and the equation, which is used to extract \boldsymbol N \mathrm {\mathbf {it}} , is modified to extract separated \boldsymbol N \mathrm {\mathbf {it}} s in the channel and the space regions. We confirm that our method is accurate by comparing the measured \boldsymbol I \mathrm {\mathbf {CP}} with the calculated one. [ABSTRACT FROM PUBLISHER]