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Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. The main method for reducing the trench width is to design large trench angle. However large trench angle for better characteristics causes some challenges. And process window always becomes narrow to get excellent characteristic. For quality control of trench angle, we found that the wafer warpage was related to the trench angle at two process steps. We confirmed these mechanisms by simulation and experiment. Furthermore, we examined which process step was appropriate for monitoring the trench angle by wafer warpage. Finally, we acquired four correlation data related to the wafer warpage after field plate oxidation. Subsequently, we derived the regression equation for quality control and confirmed the validity of the equation. [ABSTRACT FROM AUTHOR]

In advanced field plate trench power MOSFETs (FP-MOSFETs), narrow and deep trench causes lots of challenges for process integration. Especially, process optimization for silicon in trench is the most crucial. Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. Therefore, we studied new process optimization of FP-MOSFETs with sequential phosphorus-doped silicon method, compared with “conventional” phosphorus diffusion method. We succeeded in reducing processing variations in field plates and decreasing wafer warpage by processing phosphorus-doped silicon without activation annealing. Inserting 800°C annealing before 1000°C annealing contributed no voids in silicon field plates and gates. In addition, good electrical characteristics was demonstrated with the optimized process. [ABSTRACT FROM AUTHOR]

Field-Plate (FP) MOSFET structure has field-plate and thick oxide inside each trench. Due to the field-plate effect, it can improve tradeoff between low drift layer resistance and high breakdown voltage. In this structure, silicon wafer warpage is larger than that of conventional structure. It causes various problems in production, for example an error in vacuum adsorption or wafer transportation at manufacturing tools. In order to control the wafer warpage in manufacturing process, it is necessary to understand the wafer warpage peculiar to the FP-MOSFET comprehensively. The wafer warpage of the FP-MOSFET is different in X-/Y-directions because of influence of the stripe trench pattern extending in X-direction. We predict the warpage change in a newly designed FP-MOSFET by TCAD simulation, and study the reason of the warpage peculiar to the FP-MOSFET. Particularly, we explain six significant process steps, in which the warpage is greatly changed. Moreover, three process control techniques to reduce the wafer warpage are stated. This study enabled us to control the wafer warpage in process integration for the FP-MOSFET. [ABSTRACT FROM AUTHOR]

A perfectly matched layer (PML) is commonly used in finite-difference time-domain (FDTD) simulation to absorb outgoing waves and thereby reduce artifactual reflections from the computational domain boundaries. However, previous two-dimensional studies have noted that increasing the PML loss factor does not monotonically improve the PML's performance. This paper evaluates the PML in three-dimensional FDTD acoustic simulations. It confirms the existence of an optimum loss factor, with higher values degrading PML performance. An empirical formula is offered for estimating the optimum loss factor for a linear or a quadratic profile, that depends on the PML depth, sound speed, and grid resolution. [ABSTRACT FROM AUTHOR]

Presents a study which performed magnetostriction measurements in highly-oriented melt-spun ribbons in order to investigate the lattice deformation at the spin reorientation transitions. Experimental method; Results; Discussion.