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22 results on '"Kim, Jeremie S."'

1. AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications

Author

Yahya, Jawad Haj, primary, Volos, Haris, additional, Bartolini, Davide B., additional, Antoniou, Georgia, additional, Kim, Jeremie S., additional, Wang, Zhe, additional, Kalaitzidis, Kleovoulos, additional, Rollet, Tom, additional, Chen, Zhirui, additional, Geng, Ye, additional, Mutlu, Onur, additional, and Sazeides, Yiannakis, additional

Published
2022
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2. pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

Author

Ferreira, Joao Dinis, primary, Falcao, Gabriel, additional, Gomez-Luna, Juan, additional, Alser, Mohammed, additional, Orosa, Lois, additional, Sadrosadati, Mohammad, additional, Kim, Jeremie S., additional, Oliveira, Geraldo F., additional, Shahroodi, Taha, additional, Nori, Anant, additional, and Mutlu, Onur, additional

Published
2022
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3. Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices

Author

Yağlıkçı, A. Giray, Luo, Haocong, de Oliviera, Geraldo F., Olgun, Ataberk, Patel, Minesh, Park, Jisung, Hassan, Hasan, Kim, Jeremie S., Orosa, Lois, and Mutlu, Onur

Subjects
FOS: Computer and information sciences, Hardware_MEMORYSTRUCTURES, Computer Science - Cryptography and Security, Hardware Architecture (cs.AR), Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, Computer Science - Hardware Architecture, Cryptography and Security (cs.CR)
Abstract

RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and precharging a DRAM row, and thus alternating the voltage of a row's wordline between low and high voltage levels, can cause bit flips in physically nearby rows. Recent DRAM chips are more vulnerable to RowHammer: with technology node scaling, the minimum number of activate-precharge cycles to induce a RowHammer bit flip reduces and the RowHammer bit error rate increases. Therefore, it is critical to develop effective and scalable approaches to protect modern DRAM systems against RowHammer. To enable such solutions, it is essential to develop a deeper understanding of the RowHammer vulnerability of modern DRAM chips. However, even though the voltage toggling on a wordline is a key determinant of RowHammer vulnerability, no prior work experimentally demonstrates the effect of wordline voltage (VPP) on the RowHammer vulnerability. Our work closes this gap in understanding. This is the first work to experimentally demonstrate on 272 real DRAM chips that lowering VPP reduces a DRAM chip's RowHammer vulnerability. We show that lowering VPP 1) increases the number of activate-precharge cycles needed to induce a RowHammer bit flip by up to 85.8% with an average of 7.4% across all tested chips and 2) decreases the RowHammer bit error rate by up to 66.9% with an average of 15.2% across all tested chips. At the same time, reducing VPP marginally worsens a DRAM cell's access latency, charge restoration, and data retention time within the guardbands of system-level nominal timing parameters for 208 out of 272 tested chips. We conclude that reducing VPP is a promising strategy for reducing a DRAM chip's RowHammer vulnerability without requiring modifications to DRAM chips., To appear in DSN 2022

Published
2022
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4. DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators

Author

Bostancı, F. Nisa, Olgun, Ataberk, Orosa, Lois, Yağlıkçı, A. Giray, Kim, Jeremie S., Hassan, Hasan, Ergin, Oğuz, and Mutlu, Onur

Subjects
FOS: Computer and information sciences, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture
Abstract

Random number generation is an important task in a wide variety of critical applications including cryptographic algorithms, scientific simulations, and industrial testing tools. True Random Number Generators (TRNGs) produce truly random data by sampling a physical entropy source that typically requires custom hardware and suffers from long latency. To enable high-bandwidth and low-latency TRNGs on commodity devices, recent works propose TRNGs that use DRAM as an entropy source. Although prior works demonstrate promising DRAM-based TRNGs, integration of such mechanisms into real systems poses challenges. We identify three challenges for using DRAM-based TRNGs in current systems: (1) generating random numbers can degrade system performance by slowing down concurrently-running applications due to the interference between RNG and regular memory operations in the memory controller (i.e., RNG interference), (2) this RNG interference can degrade system fairness by unfairly prioritizing applications that intensively use random numbers (i.e., RNG applications), and (3) RNG applications can experience significant slowdowns due to the high RNG latency. We propose DR-STRaNGe, an end-to-end system design for DRAM-based TRNGs that (1) reduces the RNG interference by separating RNG requests from regular requests in the memory controller, (2) improves the system fairness with an RNG-aware memory request scheduler, and (3) hides the large TRNG latencies using a random number buffering mechanism with a new DRAM idleness predictor that accurately identifies idle DRAM periods. We evaluate DR-STRaNGe using a set of 186 multiprogrammed workloads. Compared to an RNG-oblivious baseline system, DR-STRaNGe improves the average performance of non-RNG and RNG applications by 17.9% and 25.1%, respectively. DR-STRaNGe improves average system fairness by 32.1% and reduces average energy consumption by 21%.

Published
2022
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5. pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

Author

Ferreira, Joao Dinis (author), Falcao, Gabriel (author), Gomez-Luna, Juan (author), Alser, Mohammed (author), Orosa, Lois (author), Sadrosadati, Mohammad (author), Kim, Jeremie S. (author), Oliveira, Geraldo F. (author), Shahroodi, Taha (author), Ferreira, Joao Dinis (author), Falcao, Gabriel (author), Gomez-Luna, Juan (author), Alser, Mohammed (author), Orosa, Lois (author), Sadrosadati, Mohammad (author), Kim, Jeremie S. (author), Oliveira, Geraldo F. (author), and Shahroodi, Taha (author)

Abstract

Data movement between the main memory and the processor is a key contributor to execution time and energy consumption in memory-intensive applications. This data movement bottleneck can be alleviated using Processing-in-Memory (PiM). One category of PiM is Processing-using-Memory (PuM), in which computation takes place inside the memory array by exploiting intrinsic analog properties of the memory device. PuM yields high performance and energy efficiency, but existing PuM techniques support a limited range of operations. As a result, current PuM architectures cannot efficiently perform some complex operations (e.g., multiplication, division, exponentiation) without large increases in chip area and design complexity. To overcome these limitations of existing PuM architectures, we introduce pLUTo (processing-using-memory with lookup table (LUT) operations), a DRAM-based PuM architecture that leverages the high storage density of DRAM to enable the massively parallel storing and querying of lookup tables (LUTs). The key idea of pLUTo is to replace complex operations with low-cost, bulk memory reads (i.e., LUT queries) instead of relying on complex extra logic. We evaluate pLUTo across 11 real-world workloads that showcase the limitations of prior PuM approaches and show that our solution outperforms optimized CPU and GPU base-lines by an average of 713 × and 1.2 ×, respectively, while simultaneously reducing energy consumption by an average of 1855 × and 39.5 ×. Across these workloads, pLUTo outperforms state-of-the-art PiM architectures by an average of 18.3 ×. We also show that different versions of pLUTo provide different levels of flexibility and performance at different additional DRAM area overheads (between 10.2% and 23.1%). pLUTo's source code and all scripts required to reproduce the results of this paper are openly and fully available at https://github.com/CMU-SAFARI/pLUTo., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Computer Engineering

Published
2022
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11. CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations

Author

Orosa, Lois, primary, Wang, Yaohua, additional, Sadrosadati, Mohammad, additional, Kim, Jeremie S., additional, Patel, Minesh, additional, Puddu, Ivan, additional, Luo, Haocong, additional, Razavi, Kaveh, additional, Gomez-Luna, Juan, additional, Hassan, Hasan, additional, Mansouri-Ghiasi, Nika, additional, Ghose, Saugata, additional, and Mutlu, Onur, additional

Published
2021
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15. GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis

Author

Cali, Damla Senol, primary, Kalsi, Gurpreet S., additional, Bingol, Zulal, additional, Firtina, Can, additional, Subramanian, Lavanya, additional, Kim, Jeremie S., additional, Ausavarungnirun, Rachata, additional, Alser, Mohammed, additional, Gomez-Luna, Juan, additional, Boroumand, Amirali, additional, Nori, Anant, additional, Scibisz, Allison, additional, Subramoney, Sreenivas, additional, Alkan, Can, additional, Ghose, Saugata, additional, and Mutlu, Onur, additional

Published
2020
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20. RowHammer: A Retrospective.

Author

Mutlu, Onur and Kim, Jeremie S.

Subjects
*DYNAMIC random access memory, *PHASE change memory, *FLASH memory, *SCIENTIFIC literature
Abstract

This retrospective paper describes the RowHammer problem in dynamic random access memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 Conference. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called DRAM disturbance errors, which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology. Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this paper, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or phase change memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities. [ABSTRACT FROM AUTHOR]

Published
2020
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