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In this paper, we propose a detection method for Digital Radio Mondiale (DRM) Plus suitable for hybrid mode broadcasting of both DRM Plus and analog FM (Frequency Modulation) within the same frequency band. The guard-interval correlation method of Orthogonal Frequency Division Multiplexing (OFDM) is good for DRM Plus signal detection, but the false alarm possibility increases when FM signal is received. The proposed method includes a reference block in the guard-interval correlation which increases the identification rate of weak DRM Plus signals and decreases the false alarm possibility when analog FM is received. The performance of the proposed method is verified through simulations.1 [ABSTRACT FROM PUBLISHER]

The DRM Plus standard released in 2009 is a digital radio specification for radio frequency bands Band I and Band II. It is being considered in many countries as a digital replacement of analog FM broadcasting. In this paper, an implementation of the DRM Plus tuner is described using the existing FM tuner and an additional digital signal processor (DSP) for consumer radio receiver. The proposed DRM Plus tuner is implemented by using a DSP with four steps: the harmonic sampling step, the digital mixer step, poly-phase filtering step for the low pass filter, and the arbitrary sampling rate conversion step for sampling clock frequency tracking in broadcasting system. The tuner can support several interfaces for baseband part connection. Performance of the proposed tuner is verified through USB interface with satisfactory results. [ABSTRACT FROM PUBLISHER]

In this paper, we present an advanced television systems committee-mobile/handheld (ATSC-M/H) hardware multiplexer for mobile broadcasting services. The entire system consists of a processor, a pre-processor engine, memory, and external interface blocks. Specifically, we address the key design issues such as how to reduce memory access time for handling large amounts of data, how to recover from inaccurate data rates of the legacy ATSC packets, and how to synchronize various function blocks with different data rates. The proposed multiplexer simplifies interface circuits between functional blocks and reduces memory access time through simple bus arbitration. It also provides robustness against inaccurate data rates of the DTV service packets by using a rate adaptation scheme. The preprocessor engine is implemented in an FPGA device and operates at a clock speed of 40 MHz. The proposed system is fully compliant with the ATSC-M/H standard. [ABSTRACT FROM AUTHOR]