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Using an experimental AlGaN/GaN HEMT with a primary Schottky gate and three secondary MIS gates the charge trapping in the passivation layer and at the AlGaN/passivation interface layer is analyzed. The primary device is subjected to off-state drain-source voltage stress. This is followed by electrical characterization using the individual secondary gates, which allows for profiling the spatial distribution of trapped charges below the secondary gates and indicates less pronounced charge trapping towards the drain of the transistor. Experimental findings are verified by TCAD simulations. A physical equivalent network of the carrier injection and surface related trapping is proposed and experimentally verified. These novel results can be exploited for optimum field plate designs and improved compact models of HEMTs.

In this work we demonstrate a semi-empirical GaN HEMT model implemented in Verilog-A format. The model captures accurately the DC operation of test devices fabricated and measured at IMS CHIPS including the thermal effects. In addition, the off-state leakage current is physically modeled as a space-charge limited current prior to the onset of the physical breakdown. The dynamic current recovery of the transistor after stress bias is physically included by implementing the model in the form of a finite state machine, capturing the memory effect of the device. The drain current is modified to be a summation of multiple exponential terms, each corresponding to a given trapping center. This model can be used to predict the overall performance of the GaN HEMTs based on the epitaxial material composition or to infer the material composition and quality based on the measured device characteristics.