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We present a detailed study of the impact of damage minimizing patterning schemes on the electrical performance of perpendicular STT-MRAM devices at array level, compatible with 22 nm CMOS technology node. By employing a novel patterning scheme involving physical ion beam etch (IBE), etchback and oxidation steps, we show reduction in switching voltage (32%), switching energy (20%) and an improvement in the reliability window (20%), as compared to the conventional physical etch. These improvements are reported in conjunction with 10-year data retention ( $\Delta$ ), WER ∼ 1 ppm and 108 cycling on 1 kbit cells. We attribute these improvements to a significant reduction in free layer (FL) damage. Morphological studies highlighting the minimization of oxygen penetration and the subsequent bird's beak formation around the FL strongly support our understanding. These results highlight a possible tuning knob in the IBE process to improve the device performance significantly and may help to improve the tail bits.

We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V th reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).

Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec’s 300 mm CMOS fab on full wafers which clears the path for large scale integration. This proof-of-concept thus offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications.

At breakdown conditions, large current flows in STT-MRAM devices. We experimentally show that this large current causes significant self-heating of 200-300°C, which impacts the reliability extrapolation to operating conditions. By measuring and analyzing breakdown at various temperatures and on different MgO thickness, we successfully incorporate self-heating into the breakdown model. We find that the 10 year lifetime is underestimated by a factor 103 at 63-percentile, to even 107 when applying percentile scaling to 1 ppm.

For the first time, we report on 400°C compatible top-pinned perpendicular magnetic tunnel junction (MTJ) stacks with dual MgO free layer for STT-MRAM applications. Using a texture-inducing parallel-coupling barrier layer (TICPB), we enforce the pinning layer and control diffusion, which enables BEOL compatibility while keeping TMR as high as 184%. In addition, we demonstrate that using such synthetic ferro-magnetic stack (SFM) design with TICPB layer allows a free layer off-set control and a switching current of 3.8 MA/cm2 in 25 nm e-CD devices.

The nanometer thin MgO barrier and the large write currents for STT-MRAM, result in an endurance bottle neck due to oxide breakdown. In this paper we present an in-depth analysis of the impact of processing on barrier breakdown, including etch techniques (ion beam etch and reactive ion etch), post etch treatments and variations of the spacer layers in the MRAM stack. We find that variability in breakdown characteristics can be significantly reduced using an optimized etch. Secondly we propose an oxygen scavenging model to explain the different reliability behavior for various stack configurations.

We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL) GAA-NWFETs with excellent electrostatics and smaller IOFF values yield ring oscillators (RO) with substantially lower power dissipation and considerably longer BTI lifetime. Improved reliability is also obtained for extensionless vs. reference FETs with conventional junctions, at comparable device and circuit performance. In addition, a TiAl-based EWF-metal is introduced for the first time in a GAA configuration resulting in higher performing, low-V T , n-type GAA-NWFETs and single-MG 6T-SRAM cells. Noise results show no significant impact of device architecture on gate stack integrity and some benefit for JL and TiAl-based GAA-NWFETs.

The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.

Fully planar NAND Flash arrays operate with very low coupling ratio (CR), and the CR reduces even further when scaling below 20 nm half-pitch. As a consequence, they suffer from programming saturation due to excessive leakage through the intergate dielectic (IGD) if no special precautions (such as the use of high-k IGD or hybrid floating gate) are taken. In this work, we investigate the dependence on the coupling ratio of programming saturation by using a dedicated test structure: by using a device with 8 wordlines sharing the same floating gate (FG), it is possible to program this device with any arbitrarily reduced effective coupling ratio, showing which programming window can be achieved. We demonstrate that the used devices with polySi\TiN FG and HfAlO\Al 2 O 3 \HfAlO IGD stack are suitable for operation with a coupling ratio down to 35% with 4V programming window above the fresh V th . This coupling ratio corresponds to fully planar memory cells with 10 nm half-pitch, showing that programming saturation is not a showstopper for scaling down to 10nm node fully planar Flash memory cells.