18 results on '"Lee, T.L."'
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2. Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond
3. An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications
4. 28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications
5. A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM
6. BTI and Electron Trapping in Hf-based Dielectrics with Dual Metal Gates
7. BTI Reliability of Dual Metal Gate CMOSFETs with Hf-based High-k Gate Dielectrics
8. Damage-Free Low-k Treatment Verified by a Novel Microwave Measurement
9. 65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application
10. Top-gated FETs/inverters with diblock copolymer self-assembled 20 nm contact holes.
11. Relaxation-Free Strained SiGe with Super Anneal for 32nm High Performance PMOS and beyond.
12. A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications.
13. Improvement of Short-Channel Characteristics of a 0.1-µm PMOSFET With Ultralow-Temperature Nitride Spacer by Using a Novel Oxide Capped Boron Uphill Treatment.
14. P-N double quantum well resonant interband tunneling diode with peak-to-valley current ratio of 144 at room temperature.
15. A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications
16. Channel Stress Modulation and Pattern Loading Effect Minimization of Milli-Second Super Anneal for Sub-65nm High Performance SiGe CMOS.
17. 65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application.
18. Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application.
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