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This paper systematically studies high-current-induced effects, hot-carrier effects, and self-heating effects in flexible low-temperature polycrystalline-silicon thin-film transistors fabricated on polyimide. By utilizing I – V and various-frequency C – V measurements, the exact location of defects generated by the self-heating effects can be clarified. The degradation mechanism is found to originate from asymmetric negative-bias temperature instability. After clarifying this mechanism, the self-heating effects were shown to be alleviated by manipulating the fabrication of the buffer layer, thereby improving heat dissipation capabilities. [ABSTRACT FROM PUBLISHER]

This letter investigates flexible polycrystalline silicon thin film transistor performance variation due to different buffer layer thicknesses. In flexible electronics, thermal expansion stress during device fabrication is inevitable. A thicker SiO2 buffer demonstrates better endurance to thermal expansion stress from the polyimide substrate during device annealing. However, if the SiO2 buffer thickness is above a critical point, its weak heat dissipation capability causes the optimal ELA crystallization condition to shift. A thermal expansion stress simulation and TEM photos were utilized to verify performance variation. Furthermore, a similar trend was observed in electrical characteristics after negative bias temperature instability. [ABSTRACT FROM PUBLISHER]

This paper reports an InGaZnO thin-film transistor with titanium-oxide semiconductor as channel capping layer. Based on the experimental results, the titanium-oxide semiconductor has the function of not only a surface passivation layer to reduce the defect states localized at grain boundaries near source/drain contacts, but also a mobility booster to enhance electric field across channel. Compared to control IGZO TFT, the crystalline IGZO TFTs with titanium-oxide semiconductor exhibits an improved performance of a low drive voltage of <\5 V, a low threshold voltage of 1.9 V, a low sub-threshold swing of 244 mV/decade , and a high mobility of 13.7 cm^2\/V\cdot\s. The simple titanium-oxide capping process have been demonstrated in this work, which provides considerable potential for further display applications requiring a low power operation and a low-temperature fabrication. [ABSTRACT FROM PUBLISHER]

We investigate lateral-body-terminal silicon–oxide–nitride–oxide–silicon thin-film transistors (LBT SONOS TFTs) under erasing operation. These devices have superior erasing efficiency by gate as well as lateral body electrode exerting bias. The erasing mechanism of LBT SONOS TFTs has been illustrated by the energy band diagrams. Holes gain sufficient energy by the electric field in the deep-depletion region to surmount the tunneling oxide barrier because of exerting body bias under erasing operation. In addition, the lateral body terminal exerting bias can enhance the erasing efficiency and is confirmed by different erasing conditions and structures. In addition, to verify the hole current injecting from the lateral body site, the size effect of LBT SONOS TFTs is also discussed. [ABSTRACT FROM AUTHOR]

This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon–oxide–nitride–oxide–silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in off-state C–V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I–V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software. [ABSTRACT FROM PUBLISHER]

This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon–oxide–nitride–oxide–silicon structure under off -state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant on-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I–V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point. [ABSTRACT FROM AUTHOR]

In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thinfilm transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the OFF state. However, our experimental results reveal that the capacitance was related with the leakage current and that it was dependent with the measurement frequencies when operated at the OFF-state region. The increase of the capacitance value is verified to be due to the increase of the electron capacitance originating from a gate-induced drain-leakage (GIDL) one. Nevertheless, the GIDL-induced electron capacitance can be suppressed by employing band-to-band hot electron stress. [ABSTRACT FROM AUTHOR]