Search

Today's computing architectures and device technologies are incapable of meeting the increasingly stringent demands on energy and performance posed by evolving applications. Therefore, alternative novel post-CMOS computing architectures are being explored. One of these is a Computation-in-Memory (CIM) architecture based on memristive devices; it integrates the processing units and the storage in the same physical location (i.e., the memory based on memristive devices). Due to their advanced manufacturing processes, use of new materials, and dual functionality, testing such chips requires specific schemes and therefore special attention. This paper describes the need for testing CIM architectures, proposes a systematic test approach, and shows the strong dependency of the test solutions on the nature of the architecture. All of these will be demonstrated using a design that is designed for computation-in-memory bit-wise logical operations.

There are a variety of purpose measuring the weight with different readability and the capacity of the weighing system, such as the using in daily life, large weight measuring instrument or laboratory dedicated high-precision digital measuring instrument. This report introduces a kind of laboratory weighing apparatus, a high-precision instrument for measuring liquid viscosity. The target weighing system readability is very sensitive, at 0.1 mg, which requires every step of making this weighing device minimizes the error. Therefore, the measuring instrument needs to use high-precision sensor, 24-bit analogue to digital converter HX711, and Arduino Uno, which is a compact and lightweight Arduino series board, has the ability to store data and perform logical operations.

Cataract is one of the leading causes of blindness, especially among older people. By the age of 80, almost half of the older population of India either have cataract or have already had a surgery for it. Surveys by WHO/NPCB suggest that there are over 12 million blind people in India out of which 80.1% of these people are blind because of cataract. It is crucial that cases of cataract are detected in its earlier stage to avoid complete blindness.In this research paper, digital image processing is used on eye images to determine the presence of cataract along with its severity. Two different image processing algorithms are applied on a dataset that consists of images of eyes having varying degrees of cataract. The first approach uses a feature extraction based automated detection algorithm. It accepts the image, preprocesses it, extracts information regarding intensity and makes classification decisions- healthy eye, mild cataract or severe cataract. Histograms are plotted for analysis. The second method determines the degree of cataract using an area based approach. Hough transform and contour detection are used to detect shapes in the image, inversion using logical operations is performed and percentage of cataract is successfully calculated. The algorithms are compared for efficiency and accuracy.

A processor-in-memory (PIM) computer architecture is any design that performs some subset of logical operations in the same location as memory. The traditional model of computing involves a processor loading data from memory to perform operations, with a bus connecting the processor and memory. While this technique works well in many situations, a growing gap between memory performance and processor performance has led some researchers to develop alternative architectures.This paper details the implementation of a PIM architecture in a soft core microcontroller used to accelerate applications limited by register file size. Using an Artix-7 FPGA, an ATmega103 microcontroller soft core is modified to include a PIM core as an accelerator. The sample application of AES encryption provides a comparison between the baseline processor and the PIM enhanced machine. AES encryption using the modified microcontroller requires 38% fewer clock cycles without relying on application specific improvements, at the expense of increased program memory size and FPGA fabric utilization.

Inversions are indispensable to build a logically complete Boolean system. However, the implementations of inversion in some nanotechnologies are expensive than the other logical operations. Therefore, the inversions optimization is of paramount interest for high-performance nanotechnology circuit design. Recently, XOR-Majority Graphs (XMGs) are used as logic representations for advanced logic synthesis. To this end, we propose an XMG optimization technique to rewrite the complemented edges while not changing its shape. The optimizations consider both majority-of-three (MAJ) nodes and exclusive-OR (XOR) nodes by using inverter propagations. The experimental results on EPFL benchmark suites show our method can achieve an average reduction of 17.3% number of inversions, which brings up to 9.8% area improvement for the implementation using Quantum-dot Cellular Automata (QCA) circuits.

Recently, ransomware attacks are on the rise hitting critical infrastructures and organizations globally. Ransomware uses advanced encryption techniques to encrypt important files on the targeted computer, then it requests payment to decrypt the encrypted files again. Therefore, the detection and prevention of ransomware attacks represent major challenges for security researchers. This research proposes a novel static-based rules ransomware detection framework. The decision rules of the proposed framework are based on static features extracted from the ransomware files. When scanned file reached rules threshold, the framework evaluates triggered rules through logical operations to assign a score for each file. Every score represents a confidence level whether this file is ransomware or not from critical to low. The proposed framework has proven that it can detect new families based on rules and logical operations with high accuracy and detection ratio

The paper considers the results of MATLAB modeling of artificial neural networks trained to perform basic logical operations: AND, OR, XOR and NOT. Below is a description of implementation of these artificial neural networks on a microcontroller by Texas Instruments family MSP430G2x, which is marketed by the manufacturer as an ultra-low power consumption device. Implementation of artificial neural networks on such an element base is not a typical task and, thus, lets the developers of digital signal processing and control systems expand their capabilities, as well as significantly reduce the costs.

Systematised classes arithmetic and logical operations and functional operations in different theoretical and numerical basis. Investigated the system characteristics of one-bit half-adder. The proposed the circuit engineering solution of synthesis of half-adder with functional completeness of inputs and outputs and maximum speed 1 mikrotakt based on logic elements AND-NOT, which simplifies their implementation on the microelectronic crystal by means of CAD.

To achieve the goal of frontal vehicle detection in night-driving condition, we propose an effective method to detect the red taillights of vehicles. The challenge is that the taillight images captured with automatic exposure typically are overexposed, which makes red color segmentation often erroneous. Instead of customizing the camera hardware to tackle this problem, we combine morphological and logical operations to extract the overexposed region in taillights, which leads to a much more reliable taillight detection scheme. Then, we develop a robust pairing process that clusters two taillight candidates into a pair that represents a vehicle. Several criteria are considered in the pairing process, including the similarities of area, shape, and height of a pair of lights. In addition, we include the temporal consistency criterion; that is, a pair of taillights should be continually detected for a certain duration of time. An energy function is used to aggregate these criteria together. Our experiments show that both the missing and false detection rates are lower than 1.5%.

We consider a class of scheduling problems that concern the routing of a set of mobile agents over the edges of an underlying guidepath network. These problems are motivated by (i) the operations of some unit-load, automated material handling systems that are employed in many contemporary production and distribution facilities, and also by (ii) the operations that take place in the physical layouts implementing the elementary logical operations that are employed in quantum computing. The presented results include (a) a systematic formulation of the considered scheduling problems as mixed integer programs (MIPs), (b) a Lagrangian relaxation of these MIP formulations, and (c) the development of a customized dual-ascent algorithm for the systematic and expedient solution of the corresponding dual problem. The latter provides lower bounds for the original MIP formulations and potentially useful information for the construction of near-optimal routing schedules for the original problems.

Fundus Image analysis is a major concern with respect to various disease detection. Diabetic retinopathy (DR) is seen in patients suffering from diabetes mellitus type 2 which leads to blindness. Fundus images are used to identify abnormalities like microaneurysms, haemorrhages, cotton wool spots, exudates, venous beading, and optic disc oedema that cause DR. Automated diagnosis of DR gives first-hand information about the disease presence, and save diabetic patients from vision loss. This paper presents a novel ensemble approach to automatically detect exudates in the fundus images. Normal background features are removed initially. Morphological operations combined with logical operations is the ensemble approach that has enhanced the detection and marking of exudates. Publicly available standard database DIARETDB1 and images of Forus Health is used to experiment the algorithm. 89.6% of specificity, 100% of sensitivity is obtained and evaluated with logistic regression classifier. Also, 89.13% of positive predictive value and 100% negative predictive value is obtained with this approach. The AUC of ROC plot obtained is 0.969.

In this paper it is proposed an universal criterion and structures for evaluating the quality of object interaction in the deterministic cyberspace through the use of only the logical operations to determine the distances between the processes and phenomena by developing high-performance parallel processors, focused on effective solving the problems of searching, pattern recognition and decision-making.

In the present paper, we consider the reaction system, which is a computational model based on biochemical reactions in living cells, and propose reaction systems for logical operations and sorting. We first propose a reaction system that executes a two-input logical operations, such as AND, OR, and XOR, and show that the reaction system works in O (1) steps. We next propose a reaction system for a compare-and-swap operation of two binary numbers of m bits. We show that the reaction system works in O (m) parallel steps using O (m) types of objects and reaction rules. We finally propose a reaction system for sorting of n binary numbers of m bits. The reaction system is based on an idea of the odd-even sort, and we show that the reaction system works in O (mn) parallel steps using O (mn) types of objects and reaction rules.

Memristor-based cell is proposed in this paper. Digital logical operations in the proposed memrsitor cell can be performed with a voltage-controlled current (VCC) source input or a current-controlled voltage (CCV) source input. The important application of the proposed memristor cell is to build memristor-based sersors, memristor cellular automaton, and memristive cellular neural networks.

By defining a partial ordering relation on vague domain of unit interval, a definition of vague sets on a lattice V(I) is given in this paper. Applying the classical extension principle, the corresponding vague logical operators defined on V(I), are constructed with fuzzy logical operators on unit interval. The representations for a general model of vague rough approximation in a vague approximation space, as well as rough vague sets a transitional form from rough sets to vague rough sets, are presented via introduction of vague logical operations. Some basic properties of vague rough sets are discussed in this context.

The unique interaction of diffraction and Kerr-nonlinearity in waveguide arrays enables the formation of self-localised light fields, so called discrete solitons (DS) [1]. They have been investigated for their application in all-optical networking applications and the idea of switching DSs at junctions of waveguide arrays has been proposed [2,3]. But also linear pulses can be deflected by DSs, so called blockers, as it has been demonstrated in one-dimensional AlGaAs arrays a few years ago [4]. However, two-dimensional structures are desirable for more sophisticated logical operations.

Any protein is a linear chain of amino acid, and under specific conditions it folds into a unique native three-dimensional structure. Based upon thermodynamical hypothesis, the native structure of a protein always achieves the global minimum of free energy. The hydrophobic-hydrophilic model for predicting the protein native structure is perhaps one of the most successful and best-studied models. The protein folding problem in the hydrophobic-hydrophilic (HP) model has been proved as an NP-complete problem. This paper is the first one in which we demonstrate that bio-molecular operations with basic logical operations can be used to solve the three dimensional protein folding problem in the HP model. In order to achieve the goal, intelligent bioinformatics logic algorithms are proposed.

Nowadays, information technologies are widely used in business. Enterprises hope to make good use of the advanced technologies to analyze customer purchase behavior for better marketing. So it has become a hot issue to find interesting customer purchase patterns in a large amount of information. This paper proposes a method of granular computing to mine interesting purchase patterns. The granule represents a set of tuples that have the same attribute value in the database. For all tuples involved in interesting purchase patterns, we can represent them by using existing granules or creating new granules by logical operations (AND or OR) among existing granules. And then we use these granules to generate interesting patterns. This method not only can improve performance efficiently without scanning database repeatedly, but it is easier to understand for users and improves process flexibility. Especially for some complicated user demands, some high-level concepts which users take interest in don't exist in the database, but we can generate new granules by OR operations to represent them. So it's very convenient to mine interesting purchase patterns using granular computing.

A memory-efficient multioutput arithmetic logic unit has been designed using a polarization-encoded optical shadow casting scheme. The authors expand the scope of special-purpose optical digital computing to more general-purpose computing. Consequently, a novel design of an arithmetic logic unit (ALU) is proposed which is capable of performing both arithmetic and logical operations. A conventional ALU architecture is followed, where the output of the ALU are generated separately. Normally, all the outputs of an ALU are not required at the same time. Thus sequential output generation is not a bottleneck. The design algorithms for identifying the source patterns, input encoding, and output mask are presented. >

The calculation load of different logical and arithmetic operations and the capabilities of several computer systems are evaluated. This analysis reveals that some limitations can be alleviated through the adoption of techniques associated with the data representation. Such techniques not only achieve more efficient management of the computational resources but also provide deeper insight into developments for future control architectures. >

Various information retrieval problems encounter time-consuming bit-counting operations. For example, to choose a rational access strategy it is necessary to repeatedly evaluate the cardinalities of retrieved sets of information items. A straightforward implementation of this procedure involves shifting of data words which makes the time of bit-counting proportional to the length of the machine word. In the suggested implementation, bit-counting is done with machine words as a whole by emulating the summation through some bitwise logical operations. It turns out, that for 32 bits this algorithm runs more than 3 times faster than conventional horizontal methods and is comparable to all other methods for typical random number cases. It is better than all methods in the worst case. In future computers, with 64-bit words and bigger the gain in speed will be correspondingly higher.

Logical operations (LOs) play an important role in the synthesis of different sources of information in intelligent processing systems (IPSs). But the formal study of these LOs has been very little; even we are not very clear about what conditions these LOs should satisfy. The paper first puts forward the general paradigm of these LOs, then raises the definitions of these LOs from the viewpoint of axioms and studies the generation of these LOs, and finally investigates the main properties of LOs. Thus the faults in existing theories about LOs have been overcome. The research shows that not only the unification of these LOs is possible and necessary in logic, but also the general paradigm of these LOs can be used to study the relationships between these LOs and design different logical operators meeting different application demands.

"HOLIAC" is the name of a family of cardboard models of information-logic machines implemented with "peekaboo" logic. "Peekaboo" logic is a representation of switching logic by a display of colored spots in punched windows in cardboard slips. The slips are pushed up or down in various configurations to represent an input statement, and the user scans the resulting display of spots to gain information with which to carry to termination the particular algorithm in use, and to read the final output statement. Holiacs can be used to demonstrate machine applications of conventional-and unconventional number systems, coding and decoding, shift register manipulations, logical operations, and residue number system computations, among other things.