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We present TAICHI, a general in-memory computing deep neural network accelerator design based on RRAM crossbar arrays heterogeneously integrated with local arithmetic units and global co-processors to allow the system to efficiently map different models while maintaining high energy efficiency and throughput. A hierarchical mesh network-on-chip is implemented to facilitate communication among clusters in TAICHI to balance reconfigurability and efficiency. Detailed deployment of the different circuit components is discussed, and the system performance is estimated at several technology nodes. The heterogeneous design also allows the system to accommodate models larger than the on-chip storage capability. [ABSTRACT FROM AUTHOR]

Stochastic Computing (SC) is a computing paradigm that allows for the low-cost and low-power computation of various arithmetic operations using stochastic bit streams and digital logic. In contrast to conventional representation schemes used within the binary domain, the sequence of bit streams in the stochastic domain is inconsequential, and computation is usually non-deterministic. In this brief, we exploit the stochasticity during switching of probabilistic Conductive Bridging RAM (CBRAM) devices to efficiently generate stochastic bit streams in order to perform Deep Learning (DL) parameter optimization, reducing the size of Multiply and Accumulate (MAC) units by 5 orders of magnitude. We demonstrate that in using a 40-nm Complementary Metal Oxide Semiconductor (CMOS) process our scalable architecture occupies 1.55mm2 and consumes approximately 167 μW when optimizing parameters of a Convolutional Neural Network (CNN) while it is being trained for a character recognition task, observing no notable reduction in accuracy post-training. [ABSTRACT FROM AUTHOR]

Self-limited and forming-free Cu-based CBRAM devices with a double Al2O3 atomic layer deposition layer (D-ALD) structure were developed. The proposed structure offers desirable properties such as forming free (${V}_{\textsf {forming}}={V}_{\textsf {SET}}$), self-limited resistive switching with very low programming current ~10 nA), high ON/ OFF ratio (> 100), and nonlinear ${I}$ – ${V}$ (NL $_{\textsf {read}}$ and NL $_{\textsf {SET}}$ ~ 10) at low resistance state. The outstanding performance of D-ALD devices was due to the HT-ALD layer that operates as both a diffusion barrier preventing over injection of Cu ions and a tunneling barrier enabling self-limited programming. [ABSTRACT FROM AUTHOR]

Neuromorphic systems using memristors as artificial synapses have attracted broad interest for energy-efficient computing applications. However, networks based on these purely passive devices can be affected by parasitic effects such as series resistance and sneak path problems. Here, we analyze the effects of parasitic factors on the performance of memristor-based neuromorphic systems. During vector-array multiplication, the line resistance can cause significant distortion of the output current and the activity of the corresponding neurons. An approach to compensate the line resistance effects based on an approximate model consisting of only few known parameters is proposed and shows excellent ability to capture the complex network behavior. During training and feature detection, the series resistance can cause significant degradation of the learned dictionary, with only a few dominant neurons being trained. Using a scaling factor based on the proposed simple model, these effects can be successfully mitigated, and the correct network operations can be restored. These results provide insight and practical measures on the parasitic effects for implementation of the neuromorphic system using memristor arrays. [ABSTRACT FROM PUBLISHER]

Characterizations of resistive switching (RS) devices, especially through direct, in situ methodologies, provide valuable information that could lead to improved insights into the device switching mechanism and device design and optimization. Here, we discuss the characterization efforts on resistive switching devices to date, with emphasis on direct transmission electron microscopy observations on conducting filament formation and growth dynamics. Other characterization techniques used in filament analysis such as spectroscopic and topographic characterizations will also be covered. In the end, we will discuss challenges to be addressed and advances that are needed to further our understanding of dynamic ionic, electronic, and structural effects involved in the RS process. [ABSTRACT FROM PUBLISHER]

To resolve the sneak leakage problem and reduce the power consumption in crossbar RRAM arrays, a Cu/Al2O3/aSi/Ta cell with self-rectifying characteristics is developed. The cell exhibits low operating current ( $\sim $ nA), high ON/OFF ratios ( > 100\times $ ), and pronounced nonlinearity. The use of low-programming-current RRAM elements avoids the current-driving capability bottleneck of selectors, while the integrated rectifying layer improves the RRAM operation reliability. Endurance of over 500 cycles with \sim 100$ ON/OFF ratio was achieved without external current compliance. Even at such low programming levels, retention over s at 100 °C can still be obtained. [ABSTRACT FROM AUTHOR]

A comprehensive analysis of write operations (SET and RESET) in a resistance-change memory (resistive random access memory) crossbar array is carried out. Three types of resistive switching memory cells-nonlinear, rectifying-SET, and rectifying-RESET-are compared with each other in terms of voltage delivery, current delivery, and power consumption. Two different write schemes, V/2 and V/3, were considered, and the V/2 write scheme is preferred due to much lower power consumption. A simple numerical method was developed that simulates entire current flows and node voltages within a crossbar array and provides a quantitative tool for the accurate analysis of crossbar arrays and guidelines for developing reliable write operation. [ABSTRACT FROM AUTHOR]

Sub-1-nA operating current conductive-bridge resistive memory devices showing pronounced rectifying behavior have been demonstrated in a cell structure consisting of Cu top electrode, atomic layer deposition Al2O3 switching film and polysilicon bottom electrode as an in-cell resistor. This ultralow current provides energy savings by minimizing write, erase, and read currents. Despite having such low currents, excellent retention, ON/OFF ratio, and endurance have been demonstrated. Devices programmed with <1-nA peak current pass 6 h retention test at 85 °C and show no significant degradation after 10 000 write/erase cycles. Due to the partially formed filament, the devices at ON-state exhibit pronounced nonlinear $I$ – $V$ and current rectification—both factors are very beneficial for RRAM array operation. Multilevel storage can be obtained by controlling the filament shape through compliance current. [ABSTRACT FROM AUTHOR]