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Here, we demonstrate a novel 2-D–3-D graphene (Gr)/MoS2/Si nanowires Schottky-NP bipolar van der Waals heterostructure, which allows the combination of the unique properties of 2-D layered materials with the proven merits of well-developed silicon technologies. Significantly, the resultant devices exhibit an ultrahigh response speed of 17 ns with a broad spectral response characteristic, which represents most fast response for 2-D transition metal dichalcogenide (TMD)-based photodetectors and is comparable to that of commercial Si photodetectors. A high responsivity of 0.6 A $\text{W}^{-{1}}$ and a detectivity of ${8}\times {10}^{{12}}$ Jones are also achieved. This result suggests a pathway for the fabrication of high-speed photodetectors based on TMDs. [ABSTRACT FROM AUTHOR]

This letter reports the first demonstration of 1-kV-class AlN Schottky barrier diodes on sapphire substrates by metal organic chemical vapor deposition. The device structure mimics the silicon-on-insulator (SOI) technology, consisting of thin $n$ -AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the devices show outstanding performances with a low turn-ON voltage of 1.2 V, a high ON/OFF ratio of \sim 10^{5} , a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. The devices also exhibit excellent thermal stability over 500 K owing to the ultra-wide bandgap of AlN. The breakdown voltage of the devices can be further improved by employing field plate, edge termination technologies, and optimizing the SOI-like device structure. This letter presents a cost-effective route to high performance AlN-based Schottky barrier diodes for high-power, high-voltage, and high-temperature applications. [ABSTRACT FROM AUTHOR]

We implement finite difference method (FDM) to calculate the optical cavity effects in InGaN micro-light-emitting diodes (LEDs) with metallic coating. The dispersion relation, mode profile, energy density W of electromagnetic field, cavity quality factor Q, and effective mode area Ae\,f\,f are theoretically investigated. The results show that although the strongest confinement of the field is achieved by surface plasmon modes at GaN/Ag interface, the energy density W is small inside the cavity, leading to a high effective mode area. Additionally, the cavity without metallic coating has the highest $Q$ factors since no metal loss is involved. These results can serve as guidelines for the design and fabrication of high efficiency and high speed LEDs for the applications of solid-state lighting and visible-light communication. [ABSTRACT FROM PUBLISHER]

We study verticalGaN p-n and Schottky power diodes with different buffer layer thicknesses grown on free-standingGaN substrates, using metalorganic chemical vapor deposition. High breakdown voltage of > 1 kV and low specific on-resistance of 3 \textm\Omega \cdot cm ^2 are achieved on GaN p-n diode with 1~\mu \textm buffer layer and 9~\mu \textm drift layer without passivation or field plate. Detailed device analysis on GaN Schottky diodes indicates that buffer layer has significant impacts on the electrical properties of drift layer and thus device performances of GaN p-n diodes. A thicker buffer layer will significantly enhance the breakdown voltages of these devices, which is possibly due to the improved material quality of drift layers with reduced defect densities. Higher doping concentration in drift layer with thicker buffer layer will, however, lower breakdown voltage. More discussions reveal improving the material quality of drift layer plays amore dominant role in achieving high breakdown GaN-on-GaN p-n and Schottky diodes with increasing buffer layer thickness. [ABSTRACT FROM PUBLISHER]

The superior low-efficiency droop performance of semipolar (20\bar2\bar1) InGaN light-emitting diodes (LEDs) makes it a hot candidate for efficient solid-state lighting and full-color displays. To unveil the mystery of this low droop and high efficiency, the emission dynamics of semipolar (20\bar2\bar1) LEDs is investigated by time-resolved and steady-state photoluminescence (PL) measurements. Much smaller carrier lifetimes (radiative and nonradiative lifetime) were obtained from semipolar (20\bar2\bar1) InGaN QWs compared with those on the c-plane samples, possibly due to the reduced quantum-confined Stark effects and smaller indium fluctuation on semipolar InGaN samples. The experimental findings indicate a much reduced excess carrier density in semipolar (20\bar2\bar1) InGaN LEDs, which will impact the device performance. Based on this, a modified ABC equation with weak phase-space-filling (PSF) effect was used to model the droop characteristics of semipolar (20\bar2\bar1) LEDs. [ABSTRACT FROM PUBLISHER]

An all-digital adaptive module for input-referred second-order intercept point (IIP2) calibration in CMOS downconverters is proposed. The proposed automatic background calibration scheme utilizes a modified least-mean-square algorithm with a variable update step to achieve fast convergence. An easily acquired and highly second-order-intermodulation-distortion-correlated reference input is used with delay estimation/optimization to improve the convergence efficiency and reduce the implementation complexity. The proposed all-digital adaptive module is implemented on a field-programmable gate array to calibrate the IIP2 of a 2.62-GHz downconverter fabricated in a 0.18-\mu\m CMOS process. With the proposed automatic background IIP2 calibration, the measured IIP2 of the CMOS downconverter is improved by 21 dB from 62 to 83 dBm, while the IIP2 calibration converges in less than 0.1 ms with a 10-MHz clock, ten times faster than the conventional adaptive algorithm. [ABSTRACT FROM AUTHOR]

Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature dependence of leakage power, circuit performance, IC package cost, and reliability. While many interconnect reliability models assume a constant temperature, this paper analyzes the effects of temporal and spatial thermal gradients on interconnect lifetime in terms of electromigration, and presents a physics-based dynamic reliability model which returns reliability equivalent temperature and current density that can be used in traditional reliability analysis tools. The model is verified with numerical simulations and reveals that blindly using the maximum temperature leads to too pessimistic lifetime estimation. Therefore, the proposed model not only increases the accuracy of reliability estimates, but also enables designers to reclaim design margin in reliability-aware design. In addition, the model is useful for improving the performance of temperature-aware runtime management by modeling system lifetime as a resource to be consumed at a stress-dependent rate. [ABSTRACT FROM AUTHOR]

The article presents the authors' views on temperature-dependent reliability models to derive the expected life time of the electronic circuits. At times the system designers use a worst-case temperature to evaluate system reliability that leads to excessive design margins. An increase in temperature in general means that the chip is consuming its lifetime more rapidly and vice versa. Also the system might engage dynamic thermal management (DTM) techniques unnecessarily. The article reflects that the effect of low-temperature can compensate for that of high temperature on reliability. Recent research on material and device reliability has shown that temperature and voltage-dependent dynamic processes also govern other failure mechanisms, such as negative-bias temperature instability and gate oxide break down. A chip's thermal characteristics include not only cross-chip spatial temperature gradients but also temporal temperature gradients for each component. Lifetime banking provides benefits to the chip by avoiding unnecessary DTM engagements while meeting expected lifetime requirements. INSETS: Dynamic thermal management.;Dynamic electromigration reliability model.;Thermal behaviors in server workloads..