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This article investigates modeling and control approaches to optimize the efficiency and power factor for discontinuous conduction mode boost power factor correction converters. First, with detailed consideration of parasitics and GaN HEMT transients, the input and output charges of the converter are exactly derived, where the rate forms the comprehensive charge rate (CCR) model. Second, based on the CCR model, the overall efficiency is derived. Since the overall efficiency is only related to the input voltage, output voltage, and switching on-time, an optimal on-time is calculated to achieve the maximum efficiency. Furthermore, with the optimal on-time, a maximum efficiency average current (MEAC) controller is proposed to regulate the input current while maintaining the maximum efficiency. With the predefined optimal on-time, a switching cycle modulation method is adopted to regulate the input current as sinusoid, which improves the power factor to unity. Finally, effectiveness of the MEAC control strategy is verified by simulations and experiments. Compared with conventional constant on-time control, it achieves an optimized efficiency and power factor over a large operation range. [ABSTRACT FROM AUTHOR]

This article reveals parasitics-induced current distortion (PCD) effect in discontinuous conduction mode boost power factor (PF) correction (PFC) converter. With consideration of parasitics, accurate inductor current is derived through total differential functions of line voltage, output voltage and duty cycle. Furthermore, the proposed current model is used to analyze PFC converter under conventional sensorless average current mode (SACM) control, which is achieved by a variable duty cycle. It is found that parasitics have considerable influence to the input current, and PCD leads to a degraded PF. In order to solve this issue, a current reshaping strategy is proposed to reduce the PCD phenomenon. Based on the damped current equations, a compensation gain is derived to reshape the input current, which reduces the current damping and distortion caused by parasitics. Both the PCD phenomenon and the current reshaping strategy are verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

For switched mode power converters, boundary conduction mode (BCM) operation is an attractive alternative to improve the bandwidth, overall size, and efficiency. In this article, a sensorless ripple current mode (SRCM) controller is proposed to achieve inductor-deviation-tolerant BCM operation for boost converter. Compared to conventional approaches with current sensing or ZCD, the proposed controller relies on a digital algorithm to ensure consistent BCM operation. The algorithm calculates on/off durations of the main switch so that the inductor current valley value converges to zero. The convergence process is proved by a damped current model with considerations of parasitics and output voltage ripple. Since the convergence is not related to the inductor value, the SRCM controller achieves inductor-deviation-tolerant BCM operation. Furthermore, to improve the power efficiency, an optimal transition condition and a compensation time are adopted to achieve valley switching (VS). Finally, both consistent BCM operation and VS are achieved by the proposed control strategy. Simulations and experimental results prove that the controller effectively improves the closed-loop stability, the robustness to inductor deviation, and the power efficiency. [ABSTRACT FROM AUTHOR]

Digital peak current mode (DPCM) control is widely used for dc–dc converters operating in continuous current mode. However, current tracking delay (CTD) in the system is normally neglected in the modeling stage, which leads to poor compensator design and degraded performance. This paper investigates CTD effect in boost converter with different DPCM controls. Based on dynamic relationship between the reference current and actual inductor current, the CTD transfer functions are derived, which improves the accuracy of small signal model. Since CTD degrades the phase margin of the system, equivalent migration of right half plane zero is proposed to model CTD effect. This method is very simple and straightforward, which facilitates the compensator design. Furthermore, two novel DPCM control strategies with minimized CTD are proposed, and they are based on duty cycle restriction and duty cycle extension, respectively. Both controls greatly reduce the CTD effect and improve the response speed. Besides, the duty cycle extension benefits from an extended pulsewidth modulation (ExPWM). This optimizes the calculation algorithm and speed, while improving the time margin for digital calculations. Combined with the proposed models and controls, the CTD effect is greatly reduced. The effectiveness is verified through detailed simulations and experiments. [ABSTRACT FROM AUTHOR]

In a sensorless predictive current controlled boost converter, parameterizing the inductor plays an important role in controller performance. In this paper, a solution for inductor parameters online identification is investigated. A small-signal injection strategy is proposed to create a transient state, and convergence problem of inductance identification in steady state can be avoided. Then, a charge balance current observer (CBCO), derived from capacitor current charging balance concept, is adopted to estimate the inductor current for inductance identification. Since inductance is not used in CBCO, current estimation is not affected by inductance identification error. Because of rank-deficient problem, instead of identifying inductor parasitic resistance solely, the inductor equivalent parasitic resistance is derived. By applying it into the conventional current observer for current control loop, the accuracy of current estimation can still be guaranteed since more parasitic effects are included. To improve the accuracy of inductance identification, a load identification method is investigated. Furthermore, the effect of the equivalent series resistance of output capacitor on the proposed algorithm is analyzed. Finally, its effectiveness is verified by experimental results. [ABSTRACT FROM PUBLISHER]

A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (\sim\3.6 \ \mu\m) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme. [ABSTRACT FROM PUBLISHER]