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A 30-MHz–2.4-GHz complementary metal oxide semiconductor (CMOS) receiver with an integrated tunable RF filter and a dynamic-range-scalable energy detector for both white-space and interference-level sensing in cognitive radio systems is reported. The second-order RF filter has only two stacked transistors, and its use, in combination with a subsequent harmonic rejection mixer, results in wideband interference rejection. The energy detector with programmable rectifiers provides dynamic-range (DR) scalability, enabling shared use for white-space/interference-level detection and automatic gain control. A prototype chip, fabricated using 90-nm CMOS technology, achieved over 42-dB harmonic rejection including 7th-order component without any external device, a 67-dB gain, a 5–8-dB noise figure, a -11-dBm in-band third-order intercept point, and a +38-dBm second-order intercept point while drawing only 25–37 mA from a 1.2-V power supply. Multi-resolution DR-scalable spectrum sensing with a 0.2–30-MHz detection bandwidth, -83-dBm minimum sensitivity, and a 29–48-dB DR was demonstrated. [ABSTRACT FROM PUBLISHER]

A small-size on-chip transformer-based digital isolator for power control systems is proposed. With a proposed pulse generation and detection scheme that enables a 5 V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced to 1/4–1/8 that of conventional transformers. A test chip achieves a 2.5 kV isolation voltage, a 35 kV/us CMR, a 1.6 mA static current and a 250 Mbps data rate, all which are equal to or superior to those of optocouplers or conventional digital isolators. The developed technology greatly reduces the number of chips in power control systems by allowing integration of multiple isolators in a CMOS chip together with microcontrollers or gate drivers. Moreover, the high-speed low-power capability expands the application potential to include isolated serial links, controller area network (CAN), FlexRay, medical devices, displays, sensors, etc. [ABSTRACT FROM PUBLISHER]

A low-IF/zero-IF reconfigurable analog baseband IC embodying an automatic I/Q imbalance cancellation scheme is reported. The chip, which comprises a down-conversion mixer, an analog baseband filter, and a programmable gain amplifier, achieves a high image rejection of 55 dB without any calibration. It operates over a wide radio frequency range of 0.4–2.4 GHz, and has a cut-off frequency range of 0.3–30 MHz in zero-intermediate frequency (IF) mode and an IF range of 0.2–6 MHz in low-IF mode. The circuit in the receiver chain draws only 4.5–6.2 mA, and the clock generator including LO buffers draws 1.8–6.3 mA from a 1.2-V supply. The chip, implemented in 90-nm CMOS technology, occupies an area of 1.1 \mm^2. [ABSTRACT FROM PUBLISHER]

A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of -\ 105~dBc/\ Hz, where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of -\ 115~dBc/\ Hz at a 1-MHz offset frequency. The chip core occupies 0.37 \ mm^2 and the measured power consumption is 8.1 mA from a 1.2-V power supply. [ABSTRACT FROM AUTHOR]

This paper describes a reconfigurable analog base-band (ABB) for a software-defined radio (SDR). A wide variety of filter characteristics needed for SDR can be obtained by a reconfigurable filter based on a newly developed duty-cycle controlled discrete-time transconductor. The ABB, implemented in a 90 nm CMOS process, provides second- and fourth-order Butterworth, Chebyshev, and elliptic responses with bandwidths from 400 kHz to 30 MHz. The chip draws only 12 mA and achieves a P1dB of +7 dBm with a 1.0 V supply. The input-referred integrated in-band noise is 0.31 mVrms and the die area is as small as 0.57 mm². [ABSTRACT FROM AUTHOR]

This paper describes a 0.18-µm CMOS direct-con- version dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a ΣΔ-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode—both at 2.4/5.2 GHz). A system noise figure of 15/4.2 dB, a sensitivity of -931-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively. [ABSTRACT FROM AUTHOR]

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9–5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21 dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path. [ABSTRACT FROM AUTHOR]

Presents a study that described the fabrication technique for such a high-aspect-ratio Y-shaped-gate electrode with high yield and reliability. Gate fringing capacitance simulation; Process technology; Device performances; Conclusions.

Provides information on a study that described the first successful fabrication of high-performance, 0.1-...m p+-gate pseudomorphic heterojunction-field effect transistors (HJFET). Gate capacitance simulation; Introduction of two-step dry-etching technique which compensated for the poor dry-etching resistance of polymethylmethacrylate (PMMA); Application of gate-electrode filling technique.