Search

With the emergence of ferroelectric HfO 2 - and ZrO 2 -based thin films, the topic of ferroelectric memories has been experiencing a renaissance. These novel ferroelectric materials promise to overcome fundamental scaling and integration roadblocks of the three basic types of ferroelectric memory concepts, FRAM, FeFET and FTJs. While the understanding of the formation of ferro- and antiferroelectric properties in HfO 2 - and ZrO 2 has matured in recent years, also new memory concepts have been suggested. Some represent an advancement of the three basic ferroelectric memories other enhance the performance of existing mainstream memories by incorporating (anti-)ferroelectric layers. The present work gives an overview of these different concepts. The CMOS compatibility allows for a large variety of device architectures, which can address the entire spectrum from mass storage to chache memory. There is a serious industry drive with demonstrators up to array level and most concepts are remarkably close to commercial state-of-the-art memories. Therefore, it seems that ferroelectric memory is finally poised to make inroads into mass markets.

Big data-based acquisition and storage system (ASS) plays an important role in the design of industrial data platform. Many big data frameworks have been integrated compression and serialization method. These methods cannot meet the needs of industrial production information management for requiring time-consuming and mass storage. Based on the existing big data frameworks, we propose an enhanced industrial big data platform in order to reduce the data processing time while requiring fewer data storage space. Specifically, this paper focuses on evaluating the impact of multiple compression and serialization methods on big data platform performance and tries to choose optimal compression and serialization methods for the industrial data platform. Compared to the methods integrated in Hadoop and Spark, the experimental results showed the data compression time of the platform has been reduced by 73.9% with a less than 96% the size of data compressed, furthermore, the data serialization time has been reduced by 80.8%. With the increasing amount of data, it takes less time to compare with benchmark methods.

Bare Machine Computing (BMC) is a paradigm used in programming applications to run on a Bare Machine. It consists of a CPU, Memory, and I/O without an Operating System and resident mass storage. It utilizes an Application Development model software that interfaces directly with the hardware. It also has potential as a powerful teaching and research tool in undergraduate STEM programs, notably Computer Engineering and Computer Science. Before the COVID-19 Pandemic, researchers used the University lab environment, and Bare Systems connected via LAN/WAN. The Pandemic restrictions put members of the research team in different locations. Hence, the researchers adopted a Remote Collaboration model of Concurrent Participation, Communication, and Development for Bare Machine to continue this research. This paper discusses the advantages and disadvantages of moving the BMC research entirely online and measures needed to address the Configuration of BMC Development Environment, Communication, Collaboration, and Diverse Skill Set. The paper covers online technical research because most literature concentrates on only online survey research's benefits and drawbacks. This paper also addresses BMC application in presenting STEM subjects to students, mainly undergraduate students. Finally, the paper includes remote research that fulfills the Department of Education (DOE) requirements of student access.

Facing the challenges of global energy resources, environmental pollution and so on, Large-scale development and utilization of clean energy is imperative. Clean energy has a strong intermittent characteristics, The simulation analysis of the faults and the recovery process of this kind of equipment also need to be carried out in large numbers. In order to meet the large-scale asymmetric fault in intermittent power generation equipment recovery curve simulation results of the process data storage requirements, the development of a rapid retrieval simulation curve library a massive data oriented, successfully applied to the simulation results of the process of data storage.This paper studies the data preprocessing, data compression, data indexing technology, efficient memory database technology, the real-time memory database of mass storage data of historical documents in the library data cache to efficient operation, so as to realize the rapid retrieval simulation curve database for massive data.

An increasing number of high-performance computing system developed on FPGA devices need access to mass storage devices for storing data, the serial ATA protocol is widely used in the modern computer systems for transferring data between the host and hard disks or solid-state drives. This paper describes the design and implementation of serial ATA physical layer core based on the Xilinx GTX transceiver. With the method of cyclically changing the GTX line rate, the SATA hard disk with different line rate can be automatically identified and linked, realizing backward compatibility. An embedded system has also been developed for validating the functionality of our SATA physical layer core. We test our physical layer core with connecting our core to both SATA3 and SATA2 hard disks. The experimental result has indicated our core can not only provide the whole functionality required by the SATA physical layer, but also utilize very few logic resources on FPGA.

Internet of Things is the newfound information architecture based on the Internet that develops interactions between objects and services in a secure and reliable environment. As the availability of many smart devices rises, secure and scalable mass storage systems for aggregate data is required in IoTs applications. In this paper, we propose a new method for storing aggregate data in IoTs by use of ( $t, n$ ) –threshold secret sharing scheme in the cloud storage. In this method, original data is divided into $t$ blocks that each block is considered as a share. This method is scalable and traceable, i.e., new data can be inserted or part of original data can be deleted, without changing shares, also cloud service providers' fault in sending invalid shares are detectable.

In this paper, we present a new technology called Nucleofiles that allows storing a huge amount of information in a very small and stable medium, the DNA. The discovery of DNA computers can be used to solve extremely complex mathematical problems because of their structure composed of silicon counterparts. DNA, or Deoxyribonucleic Acid, is the hereditary material in humans and almost all other organisms. Nearly every cell in a person’s body has the same DNA located in the cell nucleus. The DNA is the primary genetic material of all living organisms and as such, the DNA molecule found in the nucleus of all cells can hold more information in a cubic centimeter than a trillion music CDs. The presented solution that is to be a website allows users to login to the system and upload their data. The data uploaded is to be converted to D-File that is to be sent later to a DNA laboratory to be synthesized as DNA sequence. The presented solution allows users to store huge amount of data in a very stable medium; thus presenting a new generation for mass storage solving Big Data issues and contributing to Green IT.

USB 2.0 is a serial communication protocol standard which connects peripherals like keyboards, mouse, cameras, audio devices like speakers and microphones, and other electronic devices like mass storage devices. Theoretically, USB 2.0 has defined a target of high speed data rate of 480Mbps, full speed data rate of 12Mbps and low speed data rate of 1.5Mbps. Hence, there arises a need to satisfy functional and speed requirements in the design and implementation of the USB 2.0 IP. This leads towards introducing a system that analyses the IP performance matching the protocol specifications. This paper depicts application of a data rate engine for bulk transfers of USB 2.0 protocol based transfers between host and device. The data rate engine consists of traffic analyzer, data rate calculator and performance tracker. The traffic analyzer recognizes different packets of the USB 2.0 transactions while keeping track of the data flow and related information. The data rate calculator acts as a plug-in to calculate the speed of transactions, additionally assisted by display unit to keep a record of obtained results. The performance tracker helps to understand the variation in data rate with respect to different factors affecting the IP performance. The implementation of data rate engine is in SystemVerilog in Linux platform and the corresponding behavior is identified through testcase simulations.

Lithium-ion battery is energy storage devices that are currently used in many popular applications. It is necessary to predict the aging of lithium-ion single cell that constitutes a mass storage device to prevent failure or explosion. In order to predict SOH, a factors that affect the aging state of the battery can be selected as a characteristic parameter. The selected characteristic parameter is composed of the input of the Neural Network for predicting the SOH. Through the preliminary experiments, the variation of SOH of the lithium-ion battery according to the cycle was confirmed, and it can be divided in to the training data sets and prediction data sets. The training of the Neural Network was performed with the training data sets, and the SOH predicted through the Neural Network was compared with the actual data.

The increasing accuracy, power efficiency, performance, and features of micro-electro-mechanical sensors, have enabled these sensors to be used for wave measurement on a variety of buoy and other platforms that would have been impractical with previous mechanical systems. But the flexibility offered by these sensors, requires examination of the characteristics of individual platforms as wave followers and in producing an orbital motion response to wave stimulus. Fortunately enhancements that support onboard mass storage, such as those provided by the SVS-603 from SeaView Systems, have enabled the capture of complete sets of raw sensor outputs for even very long term deployments. This raw motion data can be used to retroactively examine platform specifics including their response to wave stimulus, system noise, and other considerations such as mooring effects. This paper will present recent work to build supporting utilities for exploiting the mass data produced by sensor deployments and show preliminary attempts to make use of these to gain insight into buoy hull behavior.

With the increasing number and variety of logs, the requirement of storage space is growing rapidly. Meantime, the speed and accuracy of querying in massive logs are becoming increasingly important. Although the well-built distributed storage technique solves the problem of mass storage and fast query, the cost is too high. As logs are created as the method to trace the historical operation, the requirement for query rate is not high. To balance the storage cost and query rate, this paper proposes a real-time log layering storage technique based on natural language processing. According to the characteristics of the log data, this technique is combined with the text language processing technique. It compresses the real-time log data effectively while considering the query efficiency. Firstly, the method extracts the feature of each log that flows in, which will be the type name of the log. Then, the method performs word segmentation on the log and encodes each word to store the key value pairs. Finally, the key value pairs of the log are stored in the memory, and the code of each log is stored in the database. Experiments show that this method can ensure the integrity of the data effectively, decompression time dropped to 40%, compression rate down to 35%.

Portable SSD test system inspects SSDs during final semiconductor manufacturing processes. SSD is a next-generation mass storage device. As high protocol speed required, SSD interface is being moved to PCI-Express generation4. In this study, PCI-Express Gen4.0 based Portable Test System was designed. Multiple protocols, such as SATA, SAS, and NVMe test feature is included. The equipment adopt air-cooling system rather than water cooling system for compact design to remove heat that produced during SSD test process. Portable compact design can improve SSD process time.

Onboard data handling (OBDH) system is the key to spacecraft avionics. To adapt to the harsh external space environment, traditional onboard data handling system is usually highly expensive, complex and arduous by using high quality components. Design of a compact and reconfigurable onboard data handling system based is proposed in this paper. A NOR Flash with mass storage is designed as the program memory for CPU and SRAM FPGAs. The programs of the CPU and SRAM FPGAs in this system can still be reconfigurable for the launched satellites. Rad-hard designs from the Software and hardware are adopted in the onboard data handling system to realize the performances of high reliability, anti-SEU(single event upset) effect, software reconfiguration with less mass, volume and cost. Some experimental results are shown at last in the system verification.

In the era of Information Technology (IT), IT basically refers to all forms of technology that involves electronic data in any form.It includes collection of data, storing it in proper format, processing it as well as circulation of Information. With the advancement in IT industry new peripheral devices have been evolved to store the data that can connect to a business computer terminal, especially via a USB port through devices such as Hard disk, Pen drives etc. Due to portability and accessibility, previously USB mass storage device/Pen Drive was preferred by individuals, enterprises as well as government but with the advancement of technology, there is a dark side of technology which is also increasing simultaneously in the last few years in the name of cybercrime. Various organizations have lost their sensitive or confidential information due to USB flash memory stick. Due to this, most of them banned the use of USB device. In this paper we present a solution to this data theft problem which will automatically fetch & store the Unique ID (Serial Number) of mass storage USB device/Pen drive and keep record in database to monitor registered user/device as well as anonymous device. We do recognize the patter of all connected anonymous device all over the intranet and represent it in a graphical form.

Application launch times can be reduced by using low-capacity solid-state drives (SSDs) in combination with the conventional magnetic hard disk drives (HDDs). We propose a storage tiering scheme for a logically integrated hybrid disk that eliminates the requirement to store a block-mapping table on the SSDs, as well as the need to access this table for every I/O: these characteristics distinguish our scheme from most other SSD caching and driver-level tiering schemes. A heuristic identifies the disk blocks accessed during application launches, which are then moved from HDDs to SSDs by updating file-system pointers. In experiments with eight widely used applications, launch times were reduced by an average of 56 %, and our scheme outperformed the Linux DM-Cache by 6.5% on average. Because it runs as a background process, the block migration overhead is negligible. We also propose edge-block first and shortest sequence and long seek first (SSLSF) strategies for using limited SSD space effectively. Small collections of blocks, which have to be dispatched to the device driver together, are preferentially moved to the SSD especially when those blocks incur long seek times on the HDD. This produces a large reduction in HDD seek time for a small outlay of space on the SSD. In a scenario in which only 10% of launch blocks can be migrated to the SSD, the SSLSF strategy achieves average launch times for Eclipse and LibreOffice, which are 5.8% less than those exhibited by the widely used strategy of migrating short sequences of blocks first.

The Use of Raspberry pi microcomputer nowadays is increasing rapidly in various applications and projects that require an acceptable software capability and an affordable one. One of the Raspberry pi applications is to use it as a video server. Real-time video servers are used in monitoring, as well as one-sided educational conferences. In this paper, an embedded LAN live real-time video/audio stream server is designed using the Raspberry pi programming and control capabilities. The video is captured through the Raspberry pi camera module port and is compressed and sent using a special standard that applies HTTP so that it can be received from the network. The audio is also captured using a microphone and sent with the RTP protocol. This system finds somehow solutions for high cost and complex video server systems as well as the mass storage used for such systems. This system uses a video stream of 800 × 400 at 24 frames per second. This paper recommends expanding the project to a WAN network.

Since the discovery of ferroelectricity in hafnium oxide, many development activities have been started worldwide to elaborate on its suitability for memory applications. This work summarizes and suggests ferroelectric hafnium oxide-based (FE-HfO2) memory technologies that could serve as a replacement for or addition to numerous spaces in the existing memory hierarchy. We discuss the use of ferroelectric field effect transistors (FeFET) for Cache memory up to its utilization as mass storage memory cell. The current shortcomings of the existing memory technologies are highlighted and the challenges for memory concepts based on FE-HfO2 are discussed. In total, the work illustrates that due to the fact that HfO2 has been established as the de facto standard high-k material in industry, the discovered ferroelectric properties in that same material might impact the existing memory landscape as a whole.

Magnetic hard disk drives (HDDs) store over 90% of the world’s digital data enabling the internet and economical access to data to power everything from social media to self-driving cars. Heat assisted magnetic recording (HAMR) is being developed as the next recording system for HDDs. HAMR will bring profound changes to the HDD components and architecture, incorporating laser diodes in an innovative plasmonic light delivery system into the recording heads, and novel nano-magnetic materials and layer architectures in the recording media [1]. Seagate demonstrated the promise of HAMR with a 1 -2 Tb/in2 areal density demonstration [2, 3] and the subsequent demonstration of a fully functional drive with more than 1000 write power-on hours [4, 5]. The significant progresses have been enabled by breakthroughs in media and head technology together with drive integration. With continuing development efforts in reliability and data density HAMR will serve the demand for economical hard disk drive storage solutions for the world’s ever growing data. As announced in a recent blog, Seagate is now shipping HAMR units to select customers for integration tests, and will start shipping commercial HAMR products to key customers by the end of 2018 [6]. This paper will cover the key enablers for HAMR technology to support both high areal density and linear density, which will be critical for bringing a new “S” curve for the magnetic recording industry. It will also be discussed about the challenges and breakthroughs in fundamental magnetic properties for the recording layer and near field optical transducers, to support the extension of HAMR to around 4-5 Tbit/in2.

An increasing number of high performance computing applications developed on reconfigurable platforms require access to mass storage devices for storing a large amount of data. The multi-gigabit transceivers integrated in FPGA devices allow the development of a wide range of communication protocols. The Serial ATA protocol provides a solution for accessing mass storage devices at high transfer rates. This paper describes the design and implementation of Serial ATA Gen3 Host and Device controllers on Xilinx 7-Series FPGA devices to facilitate the access of high performance and embedded applications to non-volatile storage devices, e.g. hard disk drives and solid state drives. The controllers can interface with commodity Serial ATA Gen3 storage devices and host bus adapters at a data transfer rate of 6.0 Gbps. For an increased performance, both Host and Device controllers support the Native Command Queueing (NCQ) feature set, in addition to the regular read and write commands. The experimental results demonstrate the viability of the Serial ATA Gen3 controllers and prove a sustained throughput close to the maximum theoretical data transfer rates of the Serial ATA protocol, thus having the potential of being an important building block of complex systems targeting a wide range of applications.

With development of digital signal processing, the bandwidth of underlying signal becomes broader. It requires that the acquisition system must be with high sampling rate. In this paper, we propose a design of high-speed acquisition system, which is with real time sampling rate of 5Gsps and mass storage based on PCI extension for instrument (PXI) bus. The system sampler uses multi-core analog-to-digital converter (ADC) parallel sampling and combines accurate sampling clock to have enough effective bits under the premise of ensuring high real-time sampling rate. Using Field Programmable Gate Array (FPGA) to collect high-speed samples from ADC. In FPGA, serial to parallel module decreases the data rate. In order to improve the capability of capturing transient signals, the trigger detection unit is designed to control the storage operation. In addition, the design of mass data storage enhances the ability of data acquisition system to capture high speed signals. Consequently, improve the detail analysis ability of the system. The designed system has been tested with satisfactory results.

The network with massive storage at the switching nodes can store and forward bulk data from delay-insensitive applications. Increasing storage capacity can, under some circumstances, improve network throughput, like bandwidth does. In this paper, the effects of storage and bandwidth on OCS network performance and the principles of trading storage for bandwidth are discussed. Our research indicates that bandwidth is fair to flows with different sizes and is insensitive to different mean flow durations under the same load. On the contrary, the networks with massive storage are tend to discard larger flows and have favourable blocking rate to flows with smaller mean size. These results suggest that to achieve better performance in networks with mass storage, large flows should be split before transmitted to the network. Our research also suggests that the storage is particularly useful in handling bursty traffic.

This research presents an innovative way to process queries without having to perform expensive join and set operations. We propose to store the equi-join relationships of tuples on mass storage devices, such as disks, to facilitate query processing. The equi-join relationships are captured, grouped, and stored as various tables on disks, which are collectively called the Join Core. Queries involving arbitrary legitimate sequences of equi-joins, semi-joins, outer-joins, anti-joins, unions, differences, and intersections can all be answered quickly by merely merging these tables. Without having to perform joins, memory consumptions are dramatically reduced. The Join Core can also be updated dynamically. Preliminary experimental results showed that all test queries began to generate results instantly, and many completed instantly too. The proposed methodology can be very useful for queries with complex joins of large relations, and can be even more advantageous to distributed query processing, as there are fewer or even no relations or intermediate results needed to be retrieved, generated or transferred over the networks.

This paper focus on radio spectrum utilization evaluation data analysis and processing work, firstly gives the evaluation object and content description, and then for variety architecture features' mass storage, real-time streaming and high-speed operation, designs a big data processing analysis framework, finally provides main link and details ideas of cleaning, conversion and storage, analysis, calculation and implementation of the collected massive data for technical personnel reference.

A full High Energy Physics (HEP) data analysis is divided into multiple data reduction phases. Processing within these phases is extremely time consuming, therefore intermediate results are stored in files held in mass storage systems and referenced as part of large datasets. This processing model limits what can be done with interactive data analytics. Growth in size and complexity of experimental datasets, along with emerging big data tools are beginning to cause changes to the traditional ways of doing data analyses. Use of big data tools for HEP analysis looks promising, mainly because extremely large HEP datasets can be represented and held in memory across a system, and accessed interactively by encoding an analysis using high- level programming abstractions. The mainstream tools, however, are not designed for scientific computing or for exploiting the available HPC platform features. We use an example from the Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) in Geneva, Switzerland. The LHC is the highest energy particle collider in the world. Our use case focuses on searching for new types of elementary particles explaining Dark Matter in the universe. We use HDF5 as our input data format, and Spark to implement the use case. We show the benefits and limitations of using Spark with HDF5 on Edison at NERSC.

The article presents a 180nm CMOS Radiation tolerant heterogeneous Multi-core ASIC MCT-04 as the SoC (System-on-Chip) with built-in multichannel multiprotocol SpaceFibre/ GigaSpaceWire (SpaceWire-RUS standard), SpaceWire based switch for the onboard data and Mass Storage Device management. The SoC design and architecture support Single-Event-Upset (SEU) fault-tolerant. The MCT-04 embedded networking subsystem provides multiple ports for high-rate interconnection with combination of SpaceWire/ /GigaSpaceWire (SpaceWire-RUS)/SpaceFibre links. Input and processed data streams transmitted via 1.25 Gbps four multiprotocol SpaceFibre/GigaSpaceWire links with built-in DMA controllers. Two SpaceWire links (ECSS-E-50-12C) provide data transfer bandwidth 2–400 Mbps. The MCT-04 embedded networking subsystem on the base SpaceWire/GigaSpaceWire/SpaceFibre provides a balance between external and internal data throughput especially for the multifunctional micro and nanosatellites systems.

The electrocardiogram (ECG) has become a standard tool to measure and record the electrical activities of the heart because of its low-cost and non-invasive characteristic. Applications running on smart phones or tablets have been widely used for collecting and processing ECG signals, with the prevalence and massive availability of health related mobile applications. However, these applications have the disadvantage of relative small mass storage and relative poor computing ability, especially in Human-Computer interaction user experience. To achieve rapid Heart Rate Variability (HRV) analysis based on big physiological data, a novel HRV analysis system has been developed based on LeanCloud cloud platform and web application. The cloud platform can store and process mass raw ECG signals. Computing intensive signal processing tasks were implemented in Python code. The HRV analysis results displayed on the web achieve good interactivity by using Echarts. The preliminary results demonstrate that this system have strong computing ability and good Human-Computer interaction user experience.

Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing-system performance. Although it is necessary to increase memory capacity to fill these gaps, power also increases when conventional volatile memories are used. A new nonvolatile memory for this purpose has been anticipated. Storage class memory is used to fill the second gap. Many candidates exist: ReRAM, PRAM, and 3D-cross point type with resistive change RAM. However, nonvolatile last level cache (LLC) is used to fill the first gap. Advanced STT-MRAM has achieved sub-4ns read and write accesses with perpendicular magnetic tunnel junctions (p-MTJ) [1–2]. Furthermore, mature integration processes have been developed and 8Mb STT-MRAM with sub-5ns operation has shown high reliability [3]. Moreover, because of its non-volatility, STT-MRAM can reduce operation energy by more than 81% compared to SRAM for cache [1]. This paper presents STT-MRAM-based last level cache memory (LLC) including MRAM memory core, peripherals and cache logic circuits, using novel power optimization with high-speed power gating (HS-PG),considering processor architectures and cache memory accesses. The STT-MRAM-based cache has high reliability to reduce the write-error rate with novel write-verify-write. Furthermore, a read-modify-write scheme is implemented to reduce active power without penalty. Figure 7.2.1 presents a block diagram of a 4Mb STT-MRAM based cache.

The design, implementation and testing of a data logger adaptable to different situations field measurement is presented incorporating wireless communication capability and networking devices employing non-volatile mass storage of high speed and high capacity together with new high-performance microcontrollers acquisition units and data logging, remotely operable structured. With a focus on centralized operation in PC application capable of managing the network of recorders and receive stored readings for further processing and presentation of results it is defined. Finally with three units assembled in a real situation of measuring and recording vibrations overlooking a measurement application in structures subject to vibration.

Disk drives have seen a dramatic increase in storage density over the last five decades, but to continue the growth seems difficult because of physical limitations. One promising approach to overcome the impending limit is shingled magnetic recording (SMR). It can be adopted while utilizing essentially the same physical recording mechanisms currently in use. Because of its manner of writing, a shingled write disk is unable to update a written track without overwriting neighboring tracks, potentially requiring the rewrite of all the tracks to the end of a "band" (where the end of a band is an area left unwritten to allow for a non-overlapped final track). Random reads are still possible on such devices, but the handling of writes becomes critical. We describe our recent experiences evaluating the behavior of shingled disks when used in an array configuration. We propose a novel use of SMR disks in an array with regular disks which we call RAID 4S that has the potential to improve the performance of storage systems. Our evaluation shows that RAID 4S clearly demonstrates the feasibility of using SMR disks in a RAID 4 array as it can out perform the use of SMR disks in standard RAID 4 with update in place by up to 89%.

As flash memory has advantages of high data throughput, high storage density, low power consumption and low cost, it has been widely used in the applications of high speed data acquisition and massive data storage. However, the flash chip generates bad blocks during its service life, which leads to the loss of data. Hence a bad block management in the system of flash memory array is essential to ensure the reliability of the data. The bad block management affects the storage capacity utilization, which is the main factor of the service life of the storage array. This paper introduces a new bad block management, in which each flash chip in the array has a corresponding bad block table. The computer simulation shows that the proposed scheme can improve the capacity utilization according to the size of the array.

The timeline of the events surrounding an incident being investigated is one of the most important facets to forensic investigation. As a result, sometimes it is crucial to know when a suspect USB device might have been connected or disconnected from a system .A variety of forensic artifacts associated with the insertion and removal of USB devices are located in the windows registry, event logs etc. The existing forensically important locations, methodology and techniques for determining the traces left behind by the usage of USB devices in Windows XP, Vista and Windows 7 may not be the same for upcoming versions of Windows. This work aims to mainly study the forensic artifacts related to insertion and removal time stamps of various Mass Storage Class (MSC), Media Transport Protocol (MTP) and Picture Transport Protocol (PTP) enabled USB devices in Windows 8 operating system. In this paper the Windows 8 registry and Windows event logs were mainly considered as artifacts for analysis. This research explores forensic artifacts aimed to help a forensic investigator in enumerating the first insertion and last removal time stamps of various MSC, MTP and PTP enabled USB devices in Windows 8 computing environment by demonstrating the crucial Windows 8 registry keys , event logs and related metadata.

Since large-scale and data-intensive applications have been widely deployed, there is a growing demand for high-performance storage systems to support data-intensive applications. Compared with traditional storage systems, next-generation systems will embrace dedicated processor to reduce computational load of host machines and will have hybrid combinations of different storage devices. The advent of flash-memory-based solid state disk has become a critical role in revolutionizing the storage world. However, instead of simply replacing the traditional magnetic hard disk with the solid state disk, it is believed that finding a complementary approach to corporate both of them is more challenging and attractive. This paper explores an idea of active storage, an emerging new storage configuration, in terms of the architecture and design, the parallel processing capability, the cooperation of other machines in cluster computing environment, and a disk configuration, the hybrid combination of different types of disk drives. Experimental results indicate that the proposed HcDD achieves better I/O performance and longer storage system lifespan.

In recent years, tremendous amount of traffic is delivered by the Internet. However, ground networks cannot provide communication environment to disaster areas and isolated areas such as mountain and sea. Thus, as the next generation networks, optical satellite networks have attracted much attention because of many advantages such as high capacity, disaster resistance, and large coverage. Since optical communication can increase traffic rate in comparison with radio wave, the optical satellite networks can provide high speed communication. On the other hand, optical communication is greatly influenced by the atmospheric condition, which can lead to traffic congestion. Thus, we focus on utilizing satellites with embedded mass storage device to manage large amount of traffic in the network. Since satellites embedded mass storage device can store the traffic temporary, it is possible to deliver the data when the downlink condition is more favorable. However, there are no traffic control method that effectively use mass storage device embedded in satellite while taking into account optical link between satellite and optical ground station. Therefore, in this article, we propose a new traffic control method to effectively use mass storage device embedded in satellite according to optical downlink condition between satellite and optical ground station.

The high performance and ever-increasing capacity of flash memory has led to the rapid adoption of Solid-State Disks (SSDs) in mass storage systems. In order to increase disk capacity, multi-level cells (MLC) are used in the design of SSDs, but the use of such SSDs in persistent storage systems raise concerns for users due to the low reliability of such disks. In this paper, we present a hybrid erasure-coded (EECC) architecture that incorporates ECC schemes and erasure codes to improve both performance and reliability. As weak error-correction codes have faster decoding speed than complex error correction codes (ECC), we propose the use of weak-ECC at the segment level rather than complex ECC. To compensate the reduced correction ability of weak-ECC, we use an erasure code that is striped across segments rather than pages or blocks. We use a small sized HDD to store parities so that we can leverage parallelism across multiple devices and remove the parity updates from the critical write path. We carry out simulation experiments based on Disksim to demonstrate that our proposed scheme is able reduce the SSD average read-latency by up to 31.23% and along with tolerance from double chip failures, it dramatically reduces the uncorrectable page error rate.

FPGA-based platforms allow implementing reconfigurable systems that can change functionality of portions of hardware at runtime. For this purpose, non-volatile, off-chip storage is required to hold the partial-configuration bitstreams that will be used for reconfiguration. Accessing such devices requires a high CPU usage or a dedicated hardware such as a Direct Memory Access (DMA) module, especially when reading from mass storage units using file systems. Relieving the processor from bitstreams acquisition and reconfiguration control promotes parallelism and better task scheduling. This paper presents a dedicated Intellectual Property (IP) block which efficiently retrieves bitstreams from a FAT16 formatted memory and independently performs partial reconfiguration at the highest possible speed. Three versions of the same module are proposed to enable the creation of systems capable of accessing the memory with different protocols and control units. The evaluation results show the advantages of our approach in terms of reconfiguration and reading speed, reduced area overhead, flexibility and ease of use.

Holographic data storage based on polarization techniques is proposed. Angular and shift multiplexing techniques, as well as polarization multiplexing, are developed to increase storage capacity. Some experimental results are presented.

HiSMRfs a file system with standard POSIX interface suitable for Shingled Magnetic Recording (SMR) drives, has been designed and developed. HiSMRfs can manage raw SMR drives and support random writes without remapping layer implemented inside SMR drives. To achieve high performance, HiSMRfs separates data and metadata storage, and manages them differently. Metadata is managed using in-memory tree structures and stored in a high performance random write area such as in a SSD. Data writing is done through sequential appending style and store in a SMR drive. HiSMRfs includes a file/object-based RAID module for SMR/HDD arrays. The RAID module computes parity for individual files/objects and guarantees that data and parity writing are 100% in sequential and in full stripe. HiSMRfs is also suitable for a hybrid storage system with conventional HDDs and SSDs. Two prototype systems with HiSMRfs have been developed. The performance has been tested and compared with SMRfs and Flashcache. The experimental tests show that HiSMRfs performs 25% better than SMRfs, and 11% better than Flashcache system.

Solid-state disk drives (SSDs), based on flashmemory technology, have emerged as popular alternatives to conventional magnetic hard disk drives (HDDs). There is a strong motivation to use flash-based media for digital video recording (DVR), especially in mobile and handheld devices, but the recording and playback process must be carefully designed to take into account the unique properties of SSDs in order to maximize the lifetime of the drive. This outlines features that can be added to a SSD file system to increase drive lifetime, and simulation results.

With the development of desktop virtualization technology, more and more companies begins to deploy virtual desktop. Traditional NAS and SAN storages can only support small-scale users due to network bandwidth limit and poor scalability. Another disadvantage is that NAS and SAN storages are very expensive. The distributed file systems such as GFS, PVFS, and Lustre are with low cost, high scalability and mass storage, but they are only designed for specific scenarios and can not meet the need of desktop virtualization storage. The characteristics of virtual desktop 1/0 are small random 1/0, high lOPS, snapshot needed and frequent access of the root image. Based on these 1/0 characteristics, DevStore is designed for desktop virtualization, and aims to be low cost, good scalability and performance. Experiments show that DevStore image's write performance is 70MB/s and read performance is 60MB/s in gigabit Ethernet. The snapshot time of DevStore is less than lms. DevStore is also easy to expand. Experiments also show that DevStore is better than QCOW in NFS environment and meets the desktop virtualization storage need.